FY27 Intern- Integration of a RISC-V CPU into a Cache-Coherent Emulation Platform - Sophia, 6 months
On-site · France
Core
Integrate a RISC-V CPU into a cache-coherent emulation platform and validate it on hardware emulators.
Role type
Intern, RTL/Hardware Integration Engineer
Builds
CPU-based emulation platform for system IP verification
Domain
Semiconductor, Hardware Design, RISC-V
Required skills
Verilog, VHDL, RTL simulation, C programming, Assembly, RISC-V architecture, Hardware emulation
Preferred skills
Palladium, Veloce, Cache-coherent interconnects, NoC
Technologies
VCS, ModelSim, Palladium, Veloce, RISC-V, C, Assembly
Responsibilities
Import and compile RISC-V CPU RTL, Integrate CPU and interconnect into emulation testbench, Develop or reuse boot code, Integrate RISC-V toolchain, Run RTL simulations to debug integration, Compile platform for hardware emulators and validate execution
