Principal ASIC DFT Design Engineer - Terawave
Core
Define DFT architecture and test strategy for large multi-block System on Chip (SOC) designs to ensure test quality and manufactability for the TeraWave satellite communications network.
Role type
Principal ASIC DFT Design Engineer (Senior IC)
Builds
Test infrastructure (scan, compression, BIST) and test vectors for silicon bring-up and production testing of complex digital SOCs.
Domain
Semiconductor / Space Communications / Digital SoC Design
Required skills
DFT architecture definition, scan chain insertion, memory BIST, ATE pattern generation/debugging, ATPG, test coverage analysis, yield analysis
Preferred skills
Logic BIST, IEEE 1500/1687 standards, hierarchical DFT, commercial DFT tools (Tessent, DFTMAX, Modus), test time/cost optimization
Technologies
Scan, Compression, BIST, ATE, ATPG, IEEE 1500, IEEE 1687, Tessent, DFTMAX, Modus
Responsibilities
Define DFT architecture and test strategy for large multi-block SOC designs; Author DFT specifications covering scan, compression, boundary scan, and test access mechanisms; Implement scan chain insertion, test clock control, and on chip compression logic; Design memory and logic built in self test infrastructure; Generate and validate DFT vectors for silicon bring up and production test programs; Debug ATE pattern failures and drive resolution with design and product engineering teams; Support defect analysis and yield improvement using test coverage and silicon failure data
Seniority
Principal, hands-on IC with technical leadership scope
