FY27 Intern - Softip Engineering Co-Op - Canada (4 months)
Core
Intern contributing to the design and verification of ASIC IP blocks and sub-systems for Ethernet, UALink, UEC, ESUN, CXL, and PCIe FPGAs/ASICs.
Role type
Intern ASIC verification engineer
Builds
Standards-compliant IP blocks for connectivity standards (Ethernet, UALink, UEC, ESUN, CXL, PCIe)
Domain
Semiconductor / Hardware Design
Required skills
SystemVerilog, UVM, Verilog, Python, Perl, TCL, Unix/Linux Shell scripting, Source code revisioning (SVN/CVS/RCS)
Preferred skills
Digital logic design, Verilog/VHDL programming, ASIC/FPGA flows, Debugging tools
Responsibilities
Develop and document verification environments using SystemVerilog and UVM; Develop and document designs using Verilog; Execute individual testcases against RTL; Issue and track bug reports from inception to closure; Develop scripts to augment development process; Work within a team to deliver standards-compliant IP blocks.
