ASIC Verification Engineering
928 open positions
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Senior Engineer - CPU Verification (ALU, FPU Formal and Datapath Verification) SifiveBengaluru, Karnataka, India 4d Own verification planning and execution for ALU, floating-point blocks focusing on formal and datapath verification of CPU cores.
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Stage Ingénieur : Techniques de vérification basse consommation utilisant l'UVM, les preuves formelles et les capacités de l'IA (H/F) NxpSophia-Antipolis (Valbonne) 4d Intern engineer role focused on improving digital verification of Power Management in NFC components using UVM, formal proofs, and AI exploration.
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Principal Engineer, Design Verification Engineering AnalogdevicesIndia, Bangalore, RMZ 4d Lead end-to-end design verification for complex digital SoCs, microprocessor-based designs, AI/ML accelerators, and high-speed peripherals, driving execution from planning to signoff.
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Sr/ IC Design Engineer (Design Verification)↗ Ethos Search Associates Pte LtdSingapore, S00, SG 4d Develop and review test plans, create constrained-random verification environments, and debug tests for complex DUTs to ensure pre-silicon IP/IC/SOCs meet performance specifications.
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Senior Verification Design Automation Engineer JobgetherRemote 4d Building and scaling automation infrastructure for advanced ASIC verification environments, including AI-based flows and execution environments.
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Senior Silicon Design Engineer - DFT↗ AMDSingapore, S00, SG 5d Design verification engineer focused on DFT methodologies, scan test patterns, and ATPG for next-gen SERDES IPs and SOCs.
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FPGA IP Design and Verification Engineer AlteraRegus, Madhapur 5d Performs functional logic verification of FPGA designs to ensure they meet microarchitecture specifications and uncover bugs before silicon.
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THW Client Co-op (January 2027 - Rochester, NY) CienaNew York $0k–$0k5d Design and verify digital blocks, cores, and subsystems for ASIC products and FPGA-based validation within the WaveLogic coherent engine chipsets.
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Staff Engineer BroadcomIND-Bangalore Electronic City - S1 5d Multi-skilled RTL and Verification engineer specializing in DFT for complex memory and IO subsystems.
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Product Engineer I - Verification CadenceGYEONGGI-DO (Seoul) 5d Pre-sales and technical evaluation engineer for Cadence Verification Division products, supporting sales with customer scoping, benchmarking, and training.
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Staff SOC DFT Engineer IntelMalaysia, Penang 5d Develop and implement advanced DFT/DFD methodologies for complex SoC designs to maximize test coverage, debuggability, and post-silicon efficiency.
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Sr Consultant↗ HCLTechAcrelândia, AC, BR 5d Lead a group of Junior Analysts to deliver projects within timelines by collaborating with internal/external stakeholders.
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Senior ASIC Design Verification Engineer - Slingshot HpeChippewa Falls, Wisconsin, United States of America $135k–$135k6d Senior ASIC Design Verification Engineer responsible for pre-silicon verification of HPE Slingshot interconnect ASICs for HPC and AI systems.
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CPU Memory Subsystem Verification Engineer↗ AppleAustin, TX, US $150k–$150k6d End-to-end verification of CPU/GPU/SOC memory subsystems including cache coherence protocols, Load-Store units, caches, bus interface units, and memory controllers.
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Staff Verification Engineer Renesas-ElectronicsChandler, AZ, us 7d Verification and modeling of mixed-signal Automotive power management devices, including PMICs, switching regulators, and related analog IP.
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Verification Engineer | Core Engineering JumptradingBristol 7d Design, develop, and validate complex ASIC/SoC designs for a global trading platform, ensuring robust hardware and software integration.
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ASIC Design Verification Eng II Full Time - United States CiscoSan Jose, California, US $112k–$112k8d Develop and verify ASICs for Cisco's core Switching, Routing, and Wireless products using simulation, emulation, and bring-up processes.
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Senior DFT Methodology Engineer NVIDIAUS, CA, Santa Clara $168k–$168k8d Architect and develop test methodologies to make next-generation silicon testable, debuggable, and secure from the first bring-up.
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Internship Performance Analyzis and Optimization of Python-Based Verification for C++ Models Bosch-GroupKusterdingen, BW, de 8d Analyze and optimize the performance of Python-based verification environments for C++ models in industrial hardware verification.
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Applications Engineering, Sr Staff Engineer↗ SynopsysRemote $157k–$157k9d Sr Staff Applications Engineer deploying and optimizing hardware emulation platforms (ZeBu, Palladium, Veloce) for customer ASIC/SoC verification environments.
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ASIC Design for Test (DFT) Engineer (Remote)↗ Asic North, Inc.Remote $100k–$100k9d Architect and implement Design for Test (DFT) structures for block and chip-level ASIC designs to ensure test coverage and timing validation.
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Design For Test Intern, MS - Summer 2027 MarvellSanta Clara, CA $62k–$123k9d Intern role focused on Design for Test (DFT) architecture, methodology, and verification flows for complex SoC designs in the data center, enterprise, wireless, and automotive markets.
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Senior Design Verification Engineer MicrosoftUnited States, California, Mountain View 9d Plan and execute verification of complex design IP, creating constrained-random environments and formal verification to ensure functional correctness before tape out.
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Midcore Design Verification Engineer TenstorrentRemote $100k–$100k9d Verify high-performance out-of-order RISC-V CPU cores by developing test strategies, building test environments, and debugging complex processor behaviors.
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DFT&PostSiliconValidation↗ SemidynamicsBarcelona, CT, ES 10d Define and implement DFT architectures and test strategies to ensure testability, debug capabilities, and manufacturability for high-performance SoCs or SiPs.
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SOC Design Verification Engineer – Data Center Solutions↗ QualcommSan Diego, CA, US $116k–$116k10d Verify next-generation Data Center SoCs powering AI, high-performance computing, and cloud infrastructure products.
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