DFT Engineering Director
Core
Lead the implementation and verification of advanced DFT/DFD (Design for Test/Design for Debug) techniques for low power, multi-voltage ASIC designs to reduce test cost and enhance yield.
Role type
Director, DFT Engineering
Builds
Low power, multi-voltage ASIC chips
Domain
Semiconductor / ASIC Design
Required skills
DFT/DFD methodology, scan and MBIST, gate-level simulation, pre-silicon and post-silicon debugging, coverage analysis, ATPG, fault simulation, JTAG, scan compression, at-speed testing, EDA tools
Preferred skills
Core-based test methodology, scan isolation, fault models (Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, Cell Aware), DFT implementation and validation
Responsibilities
Deploy DFT methodologies, generate DFT patterns, perform coverage analysis, run and debug gate-level simulations, manage pre- and post-silicon DFT activities
Seniority
Director, strategic leadership with hands-on technical expertise
