ASIC Verification Principal Engineer
Core
Define verification architecture for Packet Forwarding switch ASICs from Module to System level and drive cross-functional alignment on networking features.
Role type
Principal ASIC Verification Engineer (Packet Forwarding Switch)
Builds
Packet Forwarding switch ASICs
Domain
Semiconductor / ASIC Design / Networking
Required skills
System Verilog, UVM, SVA, Coverage-driven methodology, Emulation, FPGA validation, Packet Forwarding switch architecture, Forwarding pipelines (L2/L3, ACLs, tunneling), Traffic management (QoS, scheduling, shaping), System-level debugging, Cross-functional leadership
Preferred skills
Merchant silicon experience, Packet Forwarding ASIC experience
Technologies
System Verilog, UVM, SVA, Emulation, FPGA
Responsibilities
Define verification architecture for Packet Forwarding switch ASICs, Drive cross-functional alignment with HW, SW, and Product teams, Drive schedule alignment with Arch and Design Team, Mentor senior technical leaders
Seniority
Principal, hands-on IC with strategic influence
