Sr Engineer, Design Verification
Core
Develop verification testbench components for chip/module level using System Verilog and UVM to achieve 100% verification completeness before tape-out.
Role type
Senior IC design verification engineer
Builds
Verification environments and testbenches for complex integrated circuits
Domain
Semiconductor / Integrated Circuit Design
Required skills
System Verilog, UVM, verification planning, code coverage, functional coverage, assertions, cover groups, silicon debugging, regression testing
Preferred skills
DDR4/DDR5/LPDDR5/DIMM protocols, Object-oriented design concepts
Technologies
System Verilog, UVM
Responsibilities
Develop verification testbench components for chip/module level; Define and execute detailed verification plans; Debug tests, regression failures, and participate in silicon debugging; Achieve 100% verification completeness before tape-out
Seniority
Senior, hands-on IC
