ASIC Verification Engineering
935 open positions
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Senior Staff Verification Engineer (DDR/LPDDR)-18604↗ SynopsysSunnyvale, CA, US $159k–$159k23d Senior verification engineer defining test plans and building UVM environments for DDR PHY and memory subsystem IP blocks.
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STAFF ENGINEER, DDEG Design Methodology MicronHyderabad - Phoenix Aquila, India 23d Lead verification and end-to-end analysis for sophisticated full-chip gate-level custom designs in advanced low-power and power management technologies (DDR4, LPDDR4, DDR5, LPDDR5) operating at high speeds up to 6400MT/s.
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Engineer II-Emulation↗ Microchip TechnologyBurnaby, BC, CA $76k–$76k23d Enable HW/FW development and co-verification of System-On-Chip (SoC) devices using industry-leading HW emulators and FPGA-based prototyping platforms.
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Senior Design Verification Engineer ON SemiconductorBrno, South Moravia, Czech Republic 23d Ensure functional correctness, quality, safety, and security of configurable RISC-V CPU IP through simulation, formal verification, and AI-assisted methods.
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Staff Engineer CPU DV SifiveHyderabad, India 23d Lead end-to-end design verification for complex CPU core microarchitectures, ensuring functional correctness, performance, and quality at the silicon level.
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CPU Core Design Verification Testbench Lead TenstorrentSanta Clara 23d Lead hands-on CPU core-level testbench development and verification for high-performance out-of-order RISC-V cores.
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Principal Digital Verification Engineer Renesas-ElectronicsDuluth, GEORGIA, us 23d Develop and verify digital sections of leading-edge memory data buffer chips (DDR5, DDR6) for datacenter AI and cloud computing applications.
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Software Engineer II MicrosoftIndia, Multiple Locations, Multiple Locations 24d Architecting and developing software to model custom silicon, hardware components, and peripherals; scaling the modeling platform from single to multiple SoCs.
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Design Verification Engineering Intern - Bachelors Texas InstrumentsDallas, TX, United States 24d Develop verification plans, test benches, and simulations for mixed-signal circuits to ensure pre-silicon verification success.
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Senior Compute Subsystem Verification Engineer↗ QualcommMarkham, ON, CA $108k–$108k24d Develop world-class multimedia and compute solutions for next-generation mobile System-on-Chips (SoCs) by creating verification environments and strategies.
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Lead Digital Verification Engineer↗ Cadence Design SystemsTown of Mount-Royal, QC, CA $90k–$166k24d Lead verification engineer developing high-performance physical IP for industry-standard protocols, focusing on digital RTL verification and reusable verification components.
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Principal Digital Verification Engineer (mfd) NxpRemote 24d Own verification of submodules including verification IPs and testbenches for ASIC/SoC designs.
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MTS Verification Engineering↗ RambusKA, IN 24d Develop verification infrastructure and test plans for complex memory interface chips (DDR) using UVM methodology to ensure design sign-off.
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DMS Verification Engineer Bosch-GroupValència, VC, es 24d Develop and execute comprehensive verification strategies for state-of-the-art Mixed-Signal SoCs by collaborating with system architects and analog/digital designers.
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Senior Silicon Verification Engineer - Bengaluru GraphcoreBengaluru 25d Ensuring RTL created by logical design matches architecture specification for Graphcore silicon through verification activities.
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DFT Design Engineer IntelIndia, Bangalore 25d Design and implement DFT solutions including scan architecture, ATPG, and memory BIST/repair for semiconductor chips.
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Lead EDA Engineer AnalogdevicesIreland, Limerick 25d Lead backend physical verification strategy and design enablement for analog and mixed-signal teams across multiple programs and advanced process nodes.
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Advanced Packaging Design Verification & Physical Validation Engineer MarvellBurlington, VT 25d Gatekeeper of design quality for advanced packaging solutions, executing physical verification flows to catch errors before tape-out.
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Senior Staff Design Verification Engineer↗ Bitdeer Development Pte. Ltd.Toa Payoh, S00, SG 25d Senior verification engineer developing and executing advanced verification methodologies for digital logic and processor architectures.
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SoC Verification Engineer↗ Ricore Technology Pte. Ltd.Clementi, S00, SG 25d Lead SoC system-level and subsystem-level verification, designing testbenches and executing plans for DMA, SMMU, clock, reset, and boot-up flows.
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Staff Verification Engineer- LoRa SemtechIND - Hyderabad 25d Define and implement test plans, develop assertion-based checkers, and perform functional verification of RTL designs using UVM methodologies to ensure completeness and quality of SoC designs.
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DMS Verification Engineer↗ BoschValencia, VC, ES 25d Develop and execute comprehensive verification strategies for state-of-the-art Mixed-Signal SoCs, collaborating with system architects and analog/digital designers.
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Design Verification Team Leader, Nitro Team
AmazonTel Aviv-Yafo, Tel Aviv, Israel
25d
Lead verification of complex SoC IO sub-systems, interconnect protocols, and hardware-software interfaces for AWS Nitro system SoC.
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Emulation Engineer↗ Maayee IncRemote, US 25d Set up and maintain emulation and prototyping platforms to support pre-silicon validation, power/performance analysis, and early software bring-up for SoC designs.
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Principal Design Verification Engineer- SerDes/PHY IP AsteralabsSan Jose $207k–$207k25d Architect and execute functional verification for high-speed SerDes/PHY IP (PMA, PCS, PHY-MAC) powering rack-scale AI infrastructure.
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Senior Design Verification Engineer - TeraWave BlueoriginCentral Texas, US $230k–$230k26d Senior Verification Engineer defining strategy and building AI-enabled verification infrastructure for TeraWave's first in-house silicon program (high-throughput modem and DSP-intensive digital beamformer).
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Senior Chip Design Verification Engineer NVIDIAIsrael, Tel Aviv 26d Build reference models, verify, and simulate performance and power management related IPs for next-generation chips.
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Senior FPGA Verification Engineer
IonQOxford, England, UK
28d
Architecting and maintaining verification environments for complex FPGA designs to support quantum control systems.
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Senior Power Management IP Verification & Validation Engineer SambanovasystemsSan Jose, CA $250k–$250k28d Verification and post-silicon validation of power management IP tightly coupled to the Reconfigurable Dataflow Unit (RDU) architecture for a full-stack generative AI platform.
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Functional Verification Engineer AccentureBengaluru 29d Develop and execute testbenches to verify the functional correctness of digital designs at the block and system level.
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ASIC Verification Engineer BroadcomUSA-CA Irvine Alton Parkway Bldg 2 29d Verify complex communication ASICs (PHYs) for high-speed interconnect products used in AI and data center networks.
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