ASIC Verification Engineering
1,768 open positions
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IC Design Engineer (Design Verification)↗ Aurexis Tech Pte. Ltd.Singapore, S00, SG 13d Develop and execute verification plans for Pre-Silicon IP/ASIC/SoC designs using SystemVerilog and UVM.
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Design Verification Engineer, DFT, RTL,SOC,↗ Diligent Tec IncSan Jose, CA, US $125k–$208k13d Validate complex electronic systems (SoC, FPGA, digital/electrical) before manufacturing through simulation, hardware testing, and root cause analysis.
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Design for Test (DFT) Engineer↗ Alphaeus Pte. Ltd.Singapore, S00, SG 13d Implement and verify Design for Test (DFT) methodologies for semiconductor IP, ASIC, and SoC designs to ensure testability and debug post-silicon failures.
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Senior Verification Engineer ArmBengaluru, India 13d Develop and own verification strategies, environments, and tests for complex IP and subsystems including high-speed I/O, PCIe, DDR, and security IP for next-generation SoCs.
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Design Verification Engineer AppleBeaverton, United States of America 13d Ensuring the quality of System on Chip (SOC) designs by developing test methodologies, test benches, and coverage plans.
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GPU HLM Engineer - Cork, Ireland↗ QualcommCork, County Cork, Ireland 13d Develop bitwise accurate functional models (C-Model) and test suites to simulate, verify, and validate next-generation Adreno GPU architectures.
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ASIC Digital Design, Sr Staff Engineer-19314↗ SynopsysMarkham, ON, CA $122k–$183k13d Senior ASIC digital verification engineer creating test plans, constrained-random/coverage-driven testbenches, and assertions for high-speed SerDes IP.
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FPGA Development Tools Engineer AlteraPenang 15, Penang, Malaysia 13d Senior Technical Lead driving development, modeling, and validation of FPGA IP and simulation models within the Altera Quartus Prime ecosystem.
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Master Thesis – Agentic AI for Stimulus Creation During Coverage Closure AxisSweden - Lund 13d Develop an Agentic AI pipeline to automate stimulus creation for ASIC verification during coverage closure, reducing manual engineering effort for hardware modules.
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Design Verification Engineer, New Grad SambanovasystemsAustin, TX $120k–$150k13d Design Verification Engineer for SambaNova's RDU (Reconfigurable Dataflow Unit) chip, building SystemVerilog and UVM environments to verify chip-level control, initialization, sequencing, and state transitions.
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Systems Design Engineer Advanced Micro Devices, IncAustin, Texas 13d Pre-silicon emulation debug, development, and validation of complex boot flows, connections, and peripherals in SOC design to validate silicon designs and implement shift left technologies.
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Principal Design Verification Engineer- SerDes/PHY IP AsteralabsSan Jose $207k13d Architect and execute functional verification for high-speed SerDes/PHY IP (PMA, PCS, PHY-MAC) powering rack-scale AI infrastructure.
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Principal DFT Engineer Renesas-ElectronicsBengaluru, KA, in 14d Own end-to-end Design-for-Test (DFT) activities for complex Automotive MCU/SoC products, driving architecture, implementation, verification, and production-test readiness.
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Senior / Staff Physical Verification CAD Engineer↗ PersolClementi, S00, SG 14d Develop and maintain DRC/LVS/ANT/ERC/LPE/ESD rule decks and implement physical verification flows for IC design.
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Staff Engineer, Digital Design Engineering↗ Analog DevicesValencia, VC, ES 14d Design complex mixed-signal integrated circuits for automotive high-speed serial data communications (GMSL SerDes) for safety and infotainment systems.
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Senior Engineer - ASIC Verification EricssonBangalore,Karnataka,India 14d Verify digital ASIC IPs for mobile network standards (5G/6G) at the block and subsystem level.
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GPU Design Verification Engineer IntelUS, California, Folsom $142k–$200k14d Verify functionality of cutting-edge graphics logic components and IPs for Intel's GPU products.
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Senior Verification Engineer - (Security IP/GPU/CPU Teams) - HYBRID - Visas Supported↗ European Tech RecruitCork, County Cork, Ireland 14d Develop performance verification tests, debug architecture bottlenecks in GPU designs, and deploy new verification methodologies using simulation and emulation.
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Senior Verification Engineer - HSIO Unit Level NVIDIAIndia, Bengaluru 14d Develop UVM-based verification test benches and methodologies for complex rapid data transfer IO IPs and sub-systems (USB, UFS, MPHY, Ethernet, MACSEC) within automotive chips.
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Senior DFT Designer NxpBangalore, IN 14d Design, implement, and verify DFT architectures for complex mixed-signal and digital SoCs to ensure robust testability and high-quality silicon.
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Ingeniero/a V&V ASIC↗ OesiaRivas-Vaciamadrid, Community of Madrid, Spain 14d Design, develop, and integrate verification solutions for high-value ASIC and SoC projects.
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Pre-Si Validation Engineer↗ Intel CorporationToronto, ON, CA CA$154k–CA$217k14d Conduct formal verification of IP and SoC microarchitecture using model checking, equivalence checking, and abstraction techniques to ensure design quality and reliability.
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ASIC DFT Engineer - Acacia (Hybrid) CiscoSan Jose, California, US $155k14d Design-for-Testability (DFT) Engineer supporting implementation, validation, and signoff for complex ASIC/SoC designs to ensure high-quality test coverage and manufacturability.
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Lead Engineer - CAD Physical Verification SilabsRemote 14d Lead Engineer for CAD Physical Verification (PV) supporting chip design and layout teams by debugging PV issues and developing verification rule decks.
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Senior Engineer, DPG LPDDR Verification MicronHyderabad, Telangana, India 14d Lead verification and end-to-end analysis of sophisticated full-chip gate-level custom designs for advanced low-power and power management technologies (DDR5, LPDDR5, DDR6, LPDDR6) operating at high speeds up to 9600MT/s.
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New College Grad - HBM VERIFICATION↗ Micron TechnologyTlaquepaque, Jalisco, Mexico 14d Provide verification support to design circuits by simulating, analyzing, and debugging pre-silicon full chip designs for HBM and emerging memory architectures.
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Junior Emulation Engineer↗ Celero CommunicationsCórdoba, X, AR 14d Junior Emulation Engineer supporting pre-silicon verification by compiling, running, and debugging RTL on hardware emulation platforms.
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Senior Digital Verification Engineer CevaBelgrade, Serbia 14d Design and implement verification environments, checkers, and testbenches in System Verilog for edge AI hardware IP (NPUs, Vision DSPs) and system-level solutions.
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VLSI ENGINEER L3 WiproHyderabad, Telangana 14d Develop VLSI systems by defining functionalities, architecture, layout, and implementation for clients, with a focus on verification and debugging.
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Ingénieur(e) Vérification Fonctionnelle FPGA/ASIC - Spatial - Toulouse Sopra-SteriaToulouse, Occitanie, fr 15d Functional verification engineer for embedded digital systems (FPGA/ASIC/SoC) in satellite communication constellations.
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