Design Verification Engineer
Core
Develop UVM/System Verilog verification environments for fabric interconnect or memory subsystems, applying formal methods and generative AI to drive quality and efficiency.
Role type
IC design verification engineer (memory/fabric interconnect)
Builds
Verification environments and test plans for silicon IP and subsystems
Domain
Semiconductor hardware design (memory controllers, fabric interconnects, coherency protocols)
Deliverable
production ML models
Required skills
UVM, System Verilog, Formal verification, Python, TypeScript, Coherent Hub Interface (CHI), AMBA, JEDEC, DFI protocols, memory controller architecture, fabric interconnects, coherency, virtualization, security, interrupts, PCIe, CXL
Preferred skills
Generative AI application in verification, product cycle knowledge from definition to silicon
Technologies
UVM, System Verilog, Python, TypeScript, Formal tools
Responsibilities
Develop integration-level verification environments, run and debug simulations, innovate verification methodologies/tools, write IP/block test plans, debug failures and achieve coverage signoff
Seniority
Mid-level IC engineer
