Senior Manager ASIC Verification
Core
Lead a team designing and verifying complex mixed-signal ICs integrating analog and digital components to ensure first-pass silicon success.
Role type
Senior Manager ASIC Verification (Mixed-Signal)
Builds
Mixed-signal ICs integrating analog and digital components
Domain
Semiconductor / Mixed-Signal IC Design
Required skills
Mixed-signal IC verification, Digital RTL design, UVM methodology, System Verilog, Testbench development, Functional coverage, Team leadership, Hiring and mentoring
Preferred skills
None stated
Technologies
System Verilog, UVM, Python, Perl, Tcl, Synthesis tools, LEC, CDC/RDC tools
Responsibilities
Architecture and design of digital blocks for CMOS ICs, Specification and RTL design with DfT concepts, Synthesis and gate-level analysis, Implementation and verification of ECOs, Develop UVM components (agents, scoreboards, environments) and assertions, Drive closure of verification metrics, Manage and mentor digital DV engineers, Drive hiring and performance reviews
Seniority
Senior, hands-on IC