ASIC Verification Engineer
Core
Develop test plans, functional coverage, and scalable verification environments for Block/Core/SOC features using System Verilog and UVM.
Role type
Senior IC ASIC Verification Engineer
Builds
Verification environments, test benches, BFMs, checkers, monitors, and scoreboards for RTL and Gatelevel simulations
Domain
Semiconductor / ASIC Design / Digital Logic Verification
Required skills
System Verilog, UVM/VMM/OVM, Object-Oriented Programming, Functional Coverage, Pseudo-random test generation, RTL debugging, Gatelevel simulation analysis
Preferred skills
PCIe, SAS, SATA protocols, AMBA AXI/AHB/APB protocols
Technologies
System Verilog, UVM, VMM, OVM, PCIe, SAS, SATA, AMBA AXI, AMBA AHB, AMBA APB
Responsibilities
Develop test plans for all features, architect scalable test benches, debug regression failures, analyze functional coverage gaps, document verification strategy
Seniority
Senior, hands-on IC
