Sr Staff Digital Verfication Engineer
Core
Designing and developing verification environments for semiconductor designs, improving verification architecture, and running simulations to ensure functionality.
Role type
Sr Staff IC verification engineer
Builds
Verification environments and testbenches for semiconductor chips
Domain
Semiconductor / Hardware Verification
Required skills
System Verilog, UVM, RTL simulation, gate-level simulation, code coverage development, test plan creation, debugging designs, object-oriented programming (C/C++/Java/Python)
Preferred skills
DDR protocol knowledge, mixed-signal verification, scripting/automation (Python), software design patterns, 100K+ lines verification environment setup
Technologies
System Verilog, UVM, Python, C/C++, Java, RTL simulators, gate-level simulators
Responsibilities
Designing and developing verification environments, improving verification architecture and flow, running RTL and gate-level simulations/regression, developing and analyzing code/functional coverage
Seniority
Sr Staff, hands-on IC
