Sr Staff System Modelling Engineer
Core
Lead the development of high-level SystemC/C++ models for Mix Signal IPs to support simulation, verification, and architectural exploration.
Role type
Sr Staff System Modelling Engineer (Hardware/SoC)
Builds
High-fidelity SystemC models of connectivity IPs (Memory, Ethernet, PCIe, UCIe) and virtual platforms
Domain
Semiconductor Hardware Engineering / SoC Design
Required skills
SystemC modeling, C/C++ programming, PCIe/Ethernet/UCIe protocols, performance analysis, architectural exploration, virtual platform integration, emulation environments, hardware/software design methodologies
Preferred skills
Mentoring junior engineers, process improvement, tool development
Technologies
SystemC, C++, C, TLM 2.0, SCV
Responsibilities
Create models of connectivity IPs using SystemC/C++ and C libraries; Perform performance analysis and architectural exploration for IP Subsystems; Test and debug models using SystemC simulation tools; Integrate models into emulation and verification environments; Integrate models into virtual platforms; Maintain and update models based on design changes; Document model interfaces; Collaborate with stakeholders on model quality; Contribute to modeling process improvements
Seniority
Sr Staff, hands-on IC with mentorship
