Lead Engineer – CAD Digital Verification
Core
Develop, enhance, and support CAD tools and EDA simulation flows for efficient verification of semiconductor products (ASIC/SoC).
Role type
Senior IC CAD Digital Verification Engineer
Builds
Scalable verification solutions, automation scripts, and simulation infrastructure for ASIC/SoC development
Domain
Semiconductor / EDA / Design Verification
Required skills
Python, Perl, Tcl, Bash, shell scripting, Verilog/SystemVerilog, UVM, RTL simulation, gate-level simulation (GLS), EDA tool integration, Linux/UNIX environments, debugging complex simulation failures
Preferred skills
Cadence SYSVIP/SYSAPI/SPA, low-power verification (UPF), DPI integration (C/C++), formal verification, functional safety, advanced coverage methodologies, AI-powered tools for productivity
Technologies
Python, Perl, Tcl, Bash, C/C++, Verilog, SystemVerilog, UVM, Cadence, Synopsys, Siemens EDA, Linux/UNIX
Responsibilities
Develop and optimize automation scripts for simulation builds and testbench generation; Collaborate with RTL designers and EDA vendors to integrate capabilities and resolve bottlenecks; Support ASIC/SoC simulation environments including RTL and gate-level simulation; Develop reusable CAD methodologies to improve verification quality and reduce turnaround time; Debug complex simulation failures and analyze coverage; Participate in technical discussions and roadmap reviews for tool enhancements
Seniority
Senior, hands-on IC
