FY27 Intern - Camera HW ASIC Verification Intern - Canada (12 or 16 months)
Core
Building UVM testbenches, test sequences, and formal assertions to verify next-generation camera chipsets and AI workflows.
Role type
Intern, ASIC Design Verification Engineer (Camera HW)
Builds
Camera chipsets and verification infrastructure for next-gen mobile connectivity
Domain
Semiconductor / Hardware Design Verification
Required skills
Verilog, System Verilog, ASIC Design Verification, Scripting
Preferred skills
UVM, C, DPI, Microprocessor architecture, Python, Perl
Technologies
UVM, Python, Perl, Formal tools
Responsibilities
Building key components of camera UVM testbench, Developing sequences and test cases to meet coverage goals, Developing formal assertions for subsystem interactions, Automating DV flows using Python/Perl, Partnering with design engineers to define verification needs
