Design Verification Engineer - Memory Controller IP
Core
Develop verification strategies and SystemVerilog/UVM environments to validate functionality, performance, and protocol behavior for next-generation Memory Controller IP.
Role type
Senior IC design verification engineer (memory controller)
Builds
High-quality Memory Controller IP for LPDDR and DDR technologies
Domain
Semiconductor / Memory Interface / SoC Design
Required skills
SystemVerilog, UVM, constrained-random testing, assertions, scoreboards, functional coverage, memory controller architecture, LPDDR/DDR protocols, RTL debugging, simulation tools
Preferred skills
LPDDR5/6, DDR5/6, DFI interfaces (4.x/5.x), AMBA protocols (AXI, ACE, CHI), verification automation scripting
Technologies
SystemVerilog, UVM, Synopsys VCS, Siemens Questa, LPDDR, DDR, DFI, AMBA
Responsibilities
Develop and maintain verification environments; Create verification plans, test scenarios, and coverage models; Debug RTL, testbench, and protocol issues; Partner with designers to resolve issues and support sign-off; Improve verification efficiency through automation.
Seniority
Senior, hands-on IC