Design Verification Engineer, Leo Payload FPGA
Core
Create and maintain UVM-based verification environments and test suites for FPGA-based subsystems to verify digital designs for networking functions in a satellite communication system.
Role type
Senior IC FPGA verification engineer
Builds
FPGA verification environments and test suites for satellite networking subsystems
Domain
Aerospace / Satellite Communications / FPGA Design
Required skills
System Verilog, UVM, FPGA verification, constrained-random testing, coverage analysis, debugging, architecture verification, SoC verification, IP block verification
Preferred skills
Python, Perl, automation scripting, networking knowledge
Technologies
System Verilog, UVM, FPGA, Python, Perl
Responsibilities
Develop configurable, self-checking testbenches; create constrained-random, metric-driven test plans; collect and analyze coverage metrics; create reusable Verification IP; mentor junior engineers; participate in development and deployment of networking and satellite bus FPGAs
Seniority
Senior, hands-on IC
