ASIC Physical Design
2,685 open positions
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Principal Physical Design CAD Engineer AsteralabsHaifa 9d Develop, maintain, and improve CAD flows and methodologies for physical design teams, supporting advanced implementation stages from synthesis through place and route, timing closure, power optimization, and signoff readiness.
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CPU Performance Architect/Modelling , Senior/Staff - Cork, Ireland↗ Qualcomm Innovation Center, Inc.Cork, County Cork, Ireland 10d Architect and design state-of-the-art CPUs focusing on performance, energy efficiency, and scalability; model advanced CPU performance features and collaborate with design teams to productize them.
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<GPU>Senior GPU Hardware Designer / GPU Digital Designer MediaTekHsinChu 10d Design and implement GPU hardware modules, including microarchitecture design, RTL coding, functional integration, and design optimization.
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FPGA Design Engineer- Cisco Silicon One CiscoCaesarea, Israel 10d Lead FPGA design and development of complex systems for next-generation networking devices and AI infrastructure.
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Atom CPU Layout Design Engineer IntelMexico, Guadalajara 10d Physical implementation of next-generation high-performance Intel Atom microprocessors, focusing on memory compilers, custom IPs, and partitions.
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Senior SoC Architect SEMRON GmbHDresden, DE (primary site) / Austin, TX 10d Lead the development of digital architecture for SoC chiplets combining SRAM, DMA, CPUs, Vector Processors, Routers, and Chiplet Communication Units for SEMRON's CapRAM™ technology enabling LLM inference.
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AI Silicon Performance Modeling and Analysis Engineer↗ Intel CorporationSanta Clara, CA, US 11d Develop and maintain performance models for next-generation AI silicon products to enable architecture exploration, design evaluation, scalability analysis, and performance projection before silicon availability.
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Chief Memory Chip Design Engineer & Architect Western-DigitalSan Jose, CA, us 11d Owns end-to-end product architecture for memory subsystems from concept through silicon qualification, acting as the final technical authority across design, process, and product engineering.
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Director of Physical Design AmbiqmicroincAustin HQ 11d Lead and scale the physical implementation organization for next-generation ultra-low-power microcontroller (MCU) products, driving the physical design roadmap to ensure world-class PPA (power, performance, area) and deliver robust silicon for high-volume…
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Senior Silicon Product Architect, Performance and Power NVIDIAUS, CA, Santa Clara 12d Define technical strategy for next-generation silicon products by connecting silicon capabilities, customer workloads, and system-level opportunities to achieve performance, power, and efficiency goals.
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Architect Delos DataPalo Alto $160k–$280k12d Define, architect, and guide the development of next-generation, high-performance ASICs for AI accelerators, networking, and datacenter computing workloads.
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Ingeniero/a FPGA junior↗ Maxwell Applied TechSantiago de Compostela, Galicia, Spain 12d Design, implement, and test FPGA modules for digital signal processing (DSP), high-speed communications, embedded software, and system-level integration.
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Principal Physical Design Engineer BroadcomUSA-CA San Jose Innovation Drive $144k12d Lead physical design implementation for next-generation high-performance networking, AI/ML accelerators, and custom cloud ASICs, transforming ultra-complex architectures into high-yielding silicon.
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Physical Design Engineer AppleCupertino, United States of America 12d Physical Design Engineer responsible for full-chip physical design flow from RTL to GDSII delivery for high-performance PHY designs.
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NoC Interconnect Design Engineer and Architect QualcommSan Diego, California, United States of America $122k–$183k12d Design and architect NoC bus components and interconnects for SoCs, defining micro-architecture, analyzing performance/power tradeoffs, and delivering RTL.
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Graduate Engineer – Systems Engineering ArmBristol, United Kingdom 12d Develop and verify system-level hardware technologies for memory management, interconnects, and AI processing within next-generation Arm-based SoCs.
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Stage - Automatisation et optimisation de Flow de Conception FPGA f/h - Strategic Student Program Siemens-EdaMeudon, FRA, France 14k12d Accelerate FPGA implementation timelines by automating and optimizing design flows using AMD Vivado DFX functions.
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Sr. Staff Engineer, Physical Design MarvellVN - Da Nang 12d Lead an experienced team of physical design and static timing analysis engineers to deliver backend design services for next-generation 5G, cloud, enterprise, and automotive SOC designs.
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Lead Product Engineer CadenceNOIDA, IN 12d Lead Product Engineer performing static timing analysis, timing closure, and ECO for advanced SoCs using industry-standard tools.
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Design Engineer AlteraBengaluru, Karnataka, India 12d Design and verify complex digital circuits for FPGA and SoC products from concept to silicon.
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Semiconductor Engineer (High-Speed Interfaces / Hardware Solutions)↗ Marquee Semiconductor Singapore Pte. Ltd.Geylang, S00, SG 12d Architect and deliver high-speed hardware solutions including PCIe Gen5/6 CEM add-in cards, slot interposers with embedded FPGA, NVMe/SSD protocol-test platforms, and multi-variant Open VPX / VNX+ Single Board Computers (SBCs) for semiconductor, memory, test…
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Staff Engineer Design InfineonBangalore BTP 12d Design and implement high-performance WLAN MAC digital systems and subsystems for next-generation semiconductor products.
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HW Designer EricssonStockholm,Stockholm,Sweden 12d Design and maintain board-level schematics for PCB/PBA products, integrating ASICs and FPGAs.
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FPGA Design Engineer BakerhughesIN-Maharashtra-Pune-7th Floor, Tower 1 & 2, Phoenix Millenium Towers S No. 132, 23. Pune-Bangalore Highway 12d Design, verification, and testing of FPGA-based modules for real-time condition monitoring systems in the energy sector.
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Senior Staff Digital Design Engineer - Audio DSP Algorithm SyntiantSchweiz 12d Design, implement, and verify DSP algorithms, interfaces, and protocols for audio processing on ASICs, supporting MEMS microphones and complex failure analyses.
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ASIC Engineer, Physical Design CAD MetaBangalore, Karnataka 12d Building and owning the physical design flow infrastructure (synthesis, place and route, timing closure) for custom AI and data center silicon.
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Lead FPGA Timing & Characterization Silicon Design Engineer AMDHyderabad, Telangana 12d Lead the development, validation, silicon correlation, and release of FPGA timing models to enable industry-leading FPGA implementation and timing analysis tools.
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Staff Engineer - DFT Marvell TechnologyBangalore, Karnataka 12d Design for Test (DFT) and Static Timing Analysis (STA) engineering for networking SoCs, covering timing constraints, testability strategy, and verification across copper and optical products.
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Solutions Architect-FPGA Advanced Micro Devices, IncSan Jose, California 12d Architect and develop hardware/software co-design solutions for FPGA-based acceleration in networking, storage, automotive, aerospace, and AI/ML workloads.
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