ASIC Physical Design
1,426 open positions
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Design Engineer II CadenceNanjing 14d Frontend Design Engineer for Advanced Physical IP Development, focusing on high-performance Consumer PHYs (eUSB2v2, USB4-PHY, PCIe, ONFI, eDP/DP, SATA) and digital RTL implementation.
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Senior Electrical Engineer MicrosoftUnited States, California, Mountain View 14d Own electrical development of custom network switch platforms from architecture through production release, translating system requirements into detailed electrical architecture and platform design specifications.
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Synthesis Engineer Ericsson ABLund, Sweden 14d Develop digital ASIC designs for Ericsson's 5G/6G mobile network infrastructure, focusing on the final critical stage before fabrication.
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Senior STA Engineer AsteralabsAhmedabad 15d Own Static Timing Analysis (STA) and timing signoff for complex ASIC/SoC designs from synthesis through tape-out.
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Principal STA Engineer GlobalFoundriesIND - Karnataka - Bengaluru - North 15d Technical authority for signoff timing convergence and shift-left strategies within the Physical Design organization for SoC closure.
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Sr Digital Physical Design Engineer↗ Keysight TechnologiesColorado Springs, CO, US $152k–$152k15d Lead full ASIC design from RTL to GDS for digital and mixed-signal chips, solving complex implementation challenges for customer applications.
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ASIC Engineering Technical Leader || Physical Design | Floor Planning | GSP & PD | Exp - 11+ years CiscoBangalore, India 15d Lead physical design implementation for next-generation networking chips in advanced process nodes, driving the flow from RTL to GDS with focus on performance and die size optimization.
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Physical Design CPU Methodology Engineer TenstorrentRemote $100k–$100k15d Define and drive implementation methodology, automation strategy, and signoff infrastructure for high-performance CPU cores across advanced process nodes.
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Staff Engineer, STA and Synthesis Renesas-ElectronicsBengaluru, KA, in 16d Ensuring robust timing closure and signoff readiness for block- and full-chip designs across all modes and corners.
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RTL Design Engineer, TPU Compute↗
GoogleAustin, TX, US
$138k–$138k16d
Design and verify custom silicon logic for Google's Tensor Processing Units (TPUs) to accelerate AI/ML workloads.
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Principal FPGA Engineer↗ Teledyne FlirRichmond, BC, CA $114k–$114k16d Define FPGA architecture strategy for next-generation industrial camera platforms, balancing performance, cost, reliability, and scalability.
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Software Engineer, Silicon Design Methodology↗ OpenAISan Francisco, CA, US $225k–$225k16d Build design methodologies, software abstractions, and infrastructure to enable rapid development of complex custom AI chips.
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Physical Design Engineer AccentureBengaluru 16d Translate logical circuit designs into physical layouts, optimizing for area, power, and timing to meet manufacturing constraints.
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SoC Physical Design Senior Manager, HBM MicronFolsom, CA, US $177k–$177k16d Lead a team of physical design and verification engineers to implement advanced HBM SoC logic/base die designs from netlist to GDSII, ensuring best-in-class PPA and robust signoff for tapeout.
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Principal FPGA Engineer FlirCanada - Richmond, BC $114k–$114k17d Define FPGA architecture strategy for next-generation industrial camera platforms, balancing performance, cost, reliability, and scalability.
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ASIC CAD Engineer, Clocks Methodology NVIDIAIndia, Bengaluru 17d Develop and validate clocking methodology solutions and custom CAD tools for next-generation heterogeneous chip designs.
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ASIC Physical Design Engineer, Senior↗ Western Camps, Inc.Remote $150k–$150k17d Senior ASIC Physical Design Engineer responsible for physical implementation of AI inference accelerators from floorplanning through tapeout.
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Senior / Lead FPGA Engineer RenishawWotton-under-Edge, UK $45k–$45k17d Design, verify, and implement FPGA architectures for next-generation additive manufacturing products, focusing on real-time processing, control, and sensing capabilities.
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Digital IC Design Engineer, Intern MarvellPavia, Italy $21k–$29k17d Design and verify high-speed parallel DSP architectures and PHY designs using CMOS technology for cloud data center and AI network infrastructure.
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HW I/P Lab Lead Samsung ElectronicsPhoenix Building, Bangalore, India 17d Lead a team in the architecture, design, and validation of next-generation purpose-specific custom hardware IP blocks.
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Staff Physical Design Engineer Enchargeai36Canada $170k–$170k17d Drive the physical implementation of next-generation semiconductor chips, translating complex microarchitectures into high-performance, power-efficient silicon.
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Senior Engineer II - Backend Implementation↗ Microchip TechnologyKA, IN 18d Backend Implementation Engineer performing Static Timing Analysis (STA) and timing closure for large System-on-Chip (SoC) designs.
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Intern in Digital RTL design and automation ON SemiconductorMarin-Epagnier, Neuchatel, Switzerland 18d Develop RTL for mix-signal state-of-the-art converters and Arithmetic Logic Units (ALU) using SystemVerilog/Verilog, and implement automation using IPXACT MESA flow.
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Senior IP Architect – Unified Intel Chassis (UIC) IP and Platform Architecture IntelIndia, Bangalore 18d Define and drive architecture specifications for Unified Intel Chassis (UIC) IP components and subsystems, ensuring implementation-aware, scalable, and power-optimized designs.
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?Senior FPGA Entwickler (m/w/d) Oberkochen, BADEN_WUERTTEMBERG 18d Designing and implementing complex FPGA solutions, creating IP cores, and verifying components for advanced technology systems.
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PD Methodology Engineer II, Annapurna Labs
AmazonCupertino, California, United States
$157k–$213k18d
Design and optimization of hardware for cloud-scale machine learning inference products like AWS Inferentia, focusing on physical design methodology and CAD flows.
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ASIC Digital Design, Staff Engineer↗ SynopsysPorto Salvo, P11, PT 18d Designing and implementing advanced ASIC digital circuits for high-performance semiconductor solutions, integrating digital and analog design principles.
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FPGA Hardware Board Design Engineer AlteraPenang 15, Penang, Malaysia 18d Lead end-to-end design and development of complex hardware platforms including processor, FPGA, and ASIC-based systems.
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Lead PPA Engineer FractileThe Crescent 19d Lead PPA Engineer responsible for driving datapath performance, power, and area (PPA) closure end-to-end for high-performance compute chips.
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FPGA Design Engineer (EAD -CPT, EAD - OPT) permitted↗ Silicon InterfacesMountain View, CA, US $62k–$62k19d Design, develop, and optimize FPGA architectures for communications and control systems, integrating them with embedded systems and conducting hardware verification.
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