Physical Design Engineer
Core
Execute block-level floorplanning, placement and route (P&R), timing closure, and physical verification for next-generation high-performance networking, AI/ML accelerators, and custom cloud ASICs on leading-edge nodes (N5/N3/N2/A14).
Role type
Junior IC physical design engineer (new college grad)
Builds
Custom ASICs for hyper-scale cloud, AI, and networking infrastructure
Domain
Semiconductor / ASIC Physical Design
Required skills
Digital CMOS logic design, Static Timing Analysis (STA), EDA tools (Cadence Innovus/Tempus, Synopsys IC Compiler II/PrimeTime), Scripting (TCL, Python, Ruby, Bash), Power grid analysis (IR drop, EM)
Preferred skills
Design for Testability (DFT), Low-power intent (UPF/CPF), FinFET technologies
Technologies
Cadence Innovus, Synopsys IC Compiler II, Synopsys PrimeTime, TCL, Python, Ruby, Bash
Responsibilities
Perform block-level floorplanning and run P&R flows; Execute Static Timing Analysis (STA) and debug timing paths; Run Physical Verification checks (DRC, LVS, ERC, Antenna) and resolve violations; Analyze IR drop and electromigration (EM) to ensure power grid integrity; Develop and maintain automated scripts to enhance flow efficiency
