Senior ASIC Design Engineer
Core
Designing digital blocks for high-performance AI infrastructure connectivity chips, owning the journey from high-level definition through RTL implementation and backend support.
Role type
Senior IC ASIC Design Engineer (Digital)
Builds
Custom connectivity solutions and standards-based chips for AI infrastructure
Domain
Semiconductor / AI Infrastructure / High-speed connectivity
Deliverable
production ML models
Required skills
Verilog, SystemVerilog, RTL coding, Micro-architecture, EDA tools (Lint, CDC, Synthesis, Timing, Power), PPA optimization, Clock Domain Crossing, Debugging
Preferred skills
DDR protocols, PCIe protocols, Power management techniques, Python scripting, Perl scripting, High-speed serial interface designs
