Stage - Automatisation et optimisation de Flow de Conception FPGA f/h - Strategic Student Program
Core
Accelerate FPGA implementation timelines by automating and optimizing design flows using AMD Vivado DFX functions.
Role type
FPGA design flow automation engineer (intern)
Builds
Automated parallel compilation pipelines for independent logic modules
Domain
Electronic design automation (EDA) / FPGA
Required skills
FPGA design flows, AMD Vivado, Tcl scripting, Python scripting, Verilog/SystemVerilog, VHDL, timing constraints (XDC), static timing analysis (STA)
Preferred skills
Microelectronics engineering background, EDA command-line interfaces
Technologies
AMD Vivado, Tcl, Python, Git
Responsibilities
Review academic/industrial literature on compilation time reduction, develop automated Tcl/Python scripts for design flow management, create independent checkpoints (DCP) and assembly checkpoints, benchmark performance metrics (compilation time, RAM usage, timing closure), document and deliver the framework in a Git repository
Seniority
Intern, Strategic Student Program
