Principal Physical Design Engineer, STA
Core
Full-Chip Static Timing Analysis (STA) Engineer ensuring high-performance ASICs meet aggressive performance targets and tight timing requirements across all operating conditions.
Role type
Principal IC physical design engineer (STA)
Builds
Custom high-performance ASICs for hyperscale cloud providers, AI platforms, and networking infrastructure
Domain
Semiconductor / ASIC Physical Design / Static Timing Analysis
Deliverable
production ML models
Required skills
Full-chip timing sign-off, SDC authoring, PrimeTime/Tempus, MMMC/OCV management, AI/ML automation in STA flows, Tcl/Python/Perl/Shell scripting, OCV/SI/IR-drop concepts, ECO generation, cross-functional collaboration
Preferred skills
Experience with 3nm/2nm nodes, 2.5D/3D chiplet integration, AI-driven methodology development
Technologies
PrimeTime, Tempus, Tcl, Python, Perl, Shell, AI/ML plugins
Responsibilities
Own final timing closure across PVT corners; Deploy AI/ML automation to minimize execution runtime and maximize infrastructure efficiency; Utilize automated workflows to triage violations and eliminate timing marginalities; Drive timing ECOs and partner cross-functionally to optimize PPA
Seniority
Principal, hands-on IC
