NoC Interconnect Design Engineer and Architect
Core
Design and architect NoC bus components and interconnects for SoCs, defining micro-architecture, analyzing performance/power tradeoffs, and delivering RTL.
Role type
Senior IC NoC Interconnect Design Engineer and Architect
Builds
Network on Chip (NoC) bus components and interconnects for System on Chips (SoCs)
Domain
Semiconductor / VLSI Design / SoC Architecture
Required skills
Bus protocols (AHB, AXI, CHI), ASIC flow (synthesis, STA, Lint), RTL design, FPGA, post-silicon debug, performance/power/area tradeoff analysis, micro-architecture definition
Preferred skills
CPU architecture knowledge
Technologies
AHB, AXI, CHI, RTL, FPGA, Synthesis tools, STA, Lint, Power tools
Responsibilities
Create micro-architecture bus component specifications, analyze performance results, deliver RTL, run tool flows, evaluate new IPs, drive protocol deployments, define system-wide guidelines for IP interoperability, support verification and silicon validation teams, work with SW teams for deployment support
Seniority
Senior, hands-on IC
