ASIC Physical Design
1,424 open positions
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TPU SoC Integration Engineer, Cloud↗
GoogleSunnyvale, CA, US
$163k–$163k10d
Lead advanced SoC integration projects for multi-chiplet TPU architecture, managing RTL hierarchy up to the package level and collaborating with ASIC Packaging/Interposer teams.
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Senior Engineer II - Physical Design↗ Microchip TechnologyBurnaby, BC, CA $86k–$86k10d Senior Physical Design Engineer executing chip development methodologies for high-performance SOCs/ASICs, including block-level place and route, physical verification, and digital wrapper development.
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TPU PCIe Design Lead↗
GoogleSunnyvale, CA, US
$192k–$192k10d
Lead PCIe microarchitecture and RTL development for Google's next-generation Tensor Processing Units (TPUs) to power AI/ML workloads in data centers.
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Die-to-Die (D2D) Applications Engineer BroadcomUSA-Colorado-Fort Collins-4380 Ziegler Road $91k–$91k10d Primary technical resource for integrating and deploying proprietary Die-to-Die (D2D) PHY IP in silicon, bridging hardware, firmware, and software for customers developing ASICs for cloud computing AI engines, supercomputers, networking, and wireless…
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Senior SoC Physical Layout & Full-Chip Integration Engineer IntelUS, Oregon, Hillsboro $122k–$232k10d Lead full-chip floorplanning, physical integration, and tapeout for advanced-node silicon development vehicles.
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Tech Lead, STA AsteralabsHyderabad 10d Own top-level timing closure and signoff for next-generation connectivity silicon powering rack-scale AI infrastructure.
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Senior FPGA Engineer DrwengAmsterdam 10d Design and implement low-latency, high-throughput FPGA applications for trading systems, managing the full development lifecycle from architecture to production support.
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Senior Staff/Principal Engineer, Digital Design (Power & Analog ICs) Renesas-ElectronicsBengaluru, KA, in 11d Architect and implement digital control, sequencing, protection, and safety logic embedded within power, analog, and mixed-signal ICs.
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Senior Engineer, Digital Design Engineering AnalogdevicesChina, Shanghai, Pudong, ZuChongzhi 11d Lead block-level digital designs and verification for complex digital systems, focusing on performance, timing closure, and power optimization.
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FPGA Development Tools Engineer - Placer AlteraToronto, Ontario, Canada $110k–$110k11d Developing and optimizing FPGA placement algorithms within the compiler toolchain to improve timing, congestion, resource utilization, and design quality.
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Sr Principal Digital Design Engineer ON SemiconductorBangalore, Karnataka, India 11d Lead digital design architecture and RTL implementation for power management ICs including LED drivers, SiC drivers, smart-switches, and efuses.
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Physical Design Engineer (RDSS Intern) NVIDIATaiwan, Hsinchu 11d VLSI physical design engineer intern responsible for netlist-to-GDSII flow, floorplanning, placement, routing, and timing/power optimization for NVIDIA chips (GeForce/Tegra/Tesla/Quadro).
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Internship: Digital Design F/M NxpCatania 11d Support digital design activities for high-impact micro-controllers (MCU) and System-on-Chip (SoC) designs within NXP's Industrial & IoT Edge solutions.
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?Senior FPGA Engineer (m/f/d) München, BAYERN 11d Lead FPGA development for engine and brake control systems in avionics, managing work packages and participating in design/verification.
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Senior ASIC Design Engineer, Low Power AI↗ QualcommMarkham, ON, CA $108k–$108k11d Design and implement ultra-low power digital audio and AI IP blocks for next-generation SoCs, focusing on power optimization and performance tradeoffs.
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Lead Design Engineer ( Synthesis/LEC/CLP ) CadenceBANGALORE, IN 11d Lead Design Engineer executing Synthesis, LEC, CLP, and power-intent flows for advanced ASIC/SoC designs.
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Physical Design Engineer OpenAISan Francisco 11d Develop tools, flows, and methodologies for physical implementation of datapath and interconnect solutions for next-generation AI accelerators.
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Sr. Staff Engineer PD GlobalFoundriesIND - Karnataka - Bengaluru - North 11d Design and implement custom silicon solutions by executing physical design flows including synthesis, place-and-route, and verification to meet customer requirements.
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Principal RTL Design Engineer, IO & Memory Systems SambanovasystemsSan Jose, CA $180k–$180k11d Design, integration, and implementation of high-speed IO and memory subsystems for the DataScale® platform to deliver reliable, high-performance AI systems at scale.
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Principal SoC Power Architect MicrosoftUnited States, Oregon, Hillsboro 11d Model processor SoC power for various workloads and generate power-constrained performance projections to inform SoC architecture definition.
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Senior Designer, Systems (Computer)↗ Starfive International Pte. Ltd.Clementi, S00, SG 12d Design, implement, and improve RTL modules for next-generation high-performance RISC-V CPU and SoC chips.
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Intern - PHY Digital Design & Automation Engineer, HBM MicronRichardson, TX 12d Develop digital design methodologies, automation frameworks, timing analysis flows, and architecture validation solutions for next-generation HBM PHY and IO subsystems.
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Senior Principal ASIC Design Engineer HpeRoseville, California, United States of America 12d Architecting and implementing high-speed ASIC subsystems for advanced networking routers and switches, defining architecture from requirements through final netlist.
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Senior FPGA Engineer↗ Search staffing services pte ltdGeylang, S00, SG 12d Develop, implement, and bring up FPGA images for SoC pre-silicon prototyping to support design verification, software development, and system test teams.
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Principal Field Application Engineer SifiveShanghai, China 12d Own and drive pre-sales technical engagement for CPU, SoC Architecture, Security, and Software/Firmware requirements, formulating solutions based on SiFive's RISC-V portfolio.
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PD Engineer, Annapurna Labs Annapurna-Labs-U-S-IncUSA $136k–$136k14d Lead block physical implementation and optimize RTL-to-GDS flows for high-performance machine learning inference hardware.
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ASIC Engineer, Annapurna Labs Amazon-Com-Services-LLCUSA $110k–$160k14d Design and optimize high-performance, area- and power-efficient RTL designs for cloud-scale machine learning inference servers.
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