ASIC Physical Design
2,685 open positions
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Sr. EMIR Analysis Engineer Advanced Micro Devices, IncBangalore, India 7d Full chip SoC electrical signoff convergence with physical design engineers to achieve first pass silicon success.
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System Performance Engineer, Senior QualcommSan Diego, California, United States of America $130k–$194k8d Research, design, develop, simulate, and validate systems-level software, hardware, architecture, and algorithms to optimize power, performance, and thermal behavior of Qualcomm Snapdragon Chipsets.
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R&D Engineering, Principal Engineer↗ SynopsysKA, IN 8d Principal Engineer responsible for timing signoff methodology, static timing analysis, and standard cell library development for advanced semiconductor nodes.
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Hardware Engineering Technical Leader CiscoBangalore, India 8d Hardware Engineering Technical Leader defining architecture, specifications, and standards for complex next-generation Cisco hardware products and systems.
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Master Thesis: Early Prediction and Optimization of power, Perfomance and Area EricssonLund,Skåne,Sweden 8d Investigate how RTL characteristics and simulation data can improve early prediction of Power, Performance, and Area (PPA) for digital designs.
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Principal Engineer Verification InfineonBangalore BTP 8d Lead digital architecture and design for Power IC product families (Gate Drivers, DC-DC Converters, PoL) from concept to mass production.
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Staff/ Senior Backend (Physical Design) Engineer↗ Amlogic Singapore Private LimitedJurong Island, S00, SG 8d Lead backend physical design tasks from netlist to GDSII, including floorplanning, P&R, timing analysis, and tape-out for advanced process nodes.
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Research And Development Engineer (FPGA)↗ UptecEindhoven Area 8d Develop FPGA-based solutions for new high-tech machine applications, translating system requirements into digital architectures and designs.
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GPU Design Engineer – Memory Hierarchy AppleSanta Clara, United States of America 8d Design and manufacture next-generation, high-performance, power-efficient processor and system-on-chip (SoC) with a focus on GPU memory hierarchy to support Apple products and services.
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Principal Engineer - FPGA/ASIC Design↗ Rolls-RoyceRemote 8d Design, verify, integrate, and test FPGA/ASIC solutions for Rolls-Royce engine control system products.
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Program Management Engineer↗ Texas InstrumentsKA, IN 8d Drive planning, execution, and delivery of complex silicon IP-related programs spanning design, licensing, and cross-functional engineering initiatives across multiple IP domain verticals.
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SoC Product Architect, Memory Ecosystem NVIDIAUS, CA, Santa Clara $320k8d Define and align NVIDIA's external memory ecosystem (DRAM, non-volatile flash) with SoC and platform roadmaps to deliver industry-leading bandwidth, latency, power, and cost.
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Senior Engineer, SoC PnP Architect ArmBengaluru, India 8d Senior SoC PnP Architect responsible for system-level performance, power, and efficiency investigations across complex silicon platforms, bridging pre-silicon modeling, emulation, and post-silicon characterization.
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Technical Lead Digital Design Engineer AsteralabsSan Jose $160k–$200k8d Design and implement next-generation digital designs for high-performance connectivity solutions, covering micro-architecture through silicon bring-up.
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RTL Engineer DensityAIUSA $215k–$300k8d Designing digital blocks and subsystems for AI accelerators from microarchitecture definition through silicon implementation.
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Ingénieur FPGA / ASIC Numérique - Industrie - Toulouse Sopra-SteriaToulouse, Occitanie, fr 8d Develop embedded and industrial systems with real-time and safety constraints, focusing on FPGA and ASIC digital circuit design.
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Concepteur.trice FPGA Go RHMontréal, Qc 8d Design, develop, integrate, and validate FPGA solutions for innovative video processing and multimedia control systems.
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Spécialiste FPGA – Secteur Défense (H/F) AltenCholet, Pays de la Loire, fr 8d Design, development, and optimization of FPGA-based solutions for critical defense applications.
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Principal Timing Design Engineer Renesas-ElectronicsKodaira, jp 8d Lead backend timing and test design for next-generation semiconductor products serving IoT, automotive, and industrial markets.
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Physical Design Engineer II MicrosoftIndia, Karnataka, Bangalore 8d Responsible for physical design implementation and integration at block, subsystem, sub-chip, and full-chip levels to develop cutting-edge semiconductor products.
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ASIC Physical Design Engineer BroadcomSingapore-Yishun 9d Design and implementation of 100 ~ 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies using commercial and in-house EDA tools.
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Silicon Physical Design Engineer V↗ Fresh ConsultingRemote 9d ASIC power analysis and optimization engineer managing power flows, signoff, and PPA optimization for digital designs.
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Sr. Tech Lead SRAM ROM Expert NxpBangalore, IN 9d Define and drive next-generation SRAM and ROM architectures for embedded and standalone memory products, including In-Memory Computing (IMC) solutions for AI/ML acceleration.
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Graduate Talent (CPU-SoC Silicon Design) IntelMalaysia, Penang 9d Design and development of next generation SOC/CPU for Intel products, including RTL validation, structural physical design, and analog IP development.
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FPGA Engineer (Mid/Intermediate Level)↗ Technica ElectronicsSant Cugat del Vallès, Catalonia, Spain 9d Design, develop, simulate, and test FPGA modules for automotive connectivity and computing applications, implementing firmware for in-house hardware platforms.
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Sr. Principal VLSI/ ASIC Design Engineer HpeSunnyvale, California, United States of America 9d Lead early-stage ASIC architecture, RTL design, and implementation for complex networking, compute, and SoC applications.
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Principal/Senior Engineer, IP Engineering GlobalFoundriesTWN - T'ai-wan - Hsinchu, TW 9d Develop high-performance compute processor IP products through planning, execution, and delivery of technical engagements and product developments.
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Senior Product Engineer - STA Siemens-EdaNoida, IND, India 9d Senior Product Engineer specializing in Static Timing Analysis (STA) and physical design flows for 7nm and 5nm semiconductor chip designs.
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