Senior Silicon Architect – Cache Coherent Interconnects
Core
Own the silicon architecture and construction plan for next-generation CPU processors, focusing on dielet partitioning, packaging, die-stacking, and floorplanning.
Role type
Senior IC silicon architect (CPU interconnects)
Builds
Next-generation CPU processors for consumer graphics, self-driving cars, and AI
Domain
Semiconductor / High-performance computing
Required skills
CPU system architecture, ASIC floor-planning, digital design, high-speed interconnects, cache coherency protocols, die-to-die interface planning, UCIe, PCIe, DRAM interfaces
Preferred skills
Advanced packaging (TSMC InFO, CoWoS, Intel EMIB), through-silicon via configurations, backside power delivery, Dielet/Interposer/Substrate connectivity
Technologies
UCIe, PCIe, DRAM, TSMC InFO, CoWoS, Intel EMIB
Responsibilities
Develop early floorplans, plan die-to-die and off-chip IO, explore 2D/2.5D/3D hybrid-bonded dielet constructions, collaborate with architecture/logic/physical design/packaging teams
Seniority
Senior, hands-on IC
