Physical Design Engineer
Core
Physical Design Engineer responsible for full-chip physical design flow from RTL to GDSII delivery for high-performance PHY designs.
Role type
Senior IC physical design engineer (PHY/SOC)
Builds
High-performance PHY and System-on-Chip (SoC) designs
Domain
Semiconductor hardware design (Physical Design)
Required skills
Static timing constraint generation, full-chip floor-planning, place and route, ECO generation, LVS/DRC verification, CAD methodology development, scripting (Perl/Tcl), SoC architecture knowledge, HDL (Verilog), STA methodology
Preferred skills
High PHY/SOC design experience, physically aware synthesis, power-grid and clock specification, physical verification debugging
Technologies
Perl, Tcl, Verilog, industry standard Physical Design & Synthesis tools
Responsibilities
Generate block/chip level static timing constraints; Build full chip floor-plan including pin placement, partitions and power grid; Perform block level place and route and close the design to meet timing, area and power constraints; Generate and Implement ECOs to fix timing, noise and EM IR violations; Run Physical Design verification flow at chip/block level and provide guidelines to fix LVS/DRC violations; Participate in establishing CAD and physical design methodologies; Assist in flow development for chip integration
Seniority
Senior, hands-on IC
