Chief Memory Chip Design Engineer & Architect
Core
Owns end-to-end product architecture for memory subsystems from concept through silicon qualification, acting as the final technical authority across design, process, and product engineering.
Role type
Senior IC Chief Memory Chip Design Engineer & Architect
Builds
Memory subsystems (DRAM, NAND/NOR, SRAM, emerging NVM) for hyperscale data centers, cloud platforms, and enterprise infrastructure.
Domain
Semiconductor / Memory IC Design
Required skills
Memory subsystem architecture, Floorplan and physical architecture, Multi-generation roadmap planning, Cross-functional trade-offs (process, circuits, DFT, packaging), Design methodology and EDA/CAD strategy, Mentorship, Executive and partner representation
Preferred skills
Embedded memory IP integration, Foundry engagement on PDKs and DTCO, Emerging NVM architecture, Standards and patents
Technologies
Cadence, Synopsys, FinFET, DFT, EDA/CAD flows
Responsibilities
Define memory subsystem architecture and design specs, Drive floorplan and physical architecture decisions, Own the multi-generation roadmap, Decide cross-functional trade-offs, Own design methodology and EDA/CAD strategy, Mentor senior and principal engineers, Represent architecture to executives and partners
Seniority
Principal, hands-on IC
