ASIC Physical Design
2,687 open positions
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ASIC Engineer CiscoSan Jose, California, US $168k–$245k14d Define, design, and take end-to-end Front-End ownership of ASIC subsystems for high-performance silicon deployed in Cisco platforms.
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Application Engineer AlteraPenang 15, Penang, Malaysia 14d Enable next-generation designs across Agilex device families by handling customer escalations, improving customer designs, and developing training materials.
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SoC Design Engineer↗ Microchip Technology Inc.Burnaby, British Columbia, Canada $86k–$186k14d Define advanced technical direction, architectures, methodologies, and reusable solutions for semiconductor architecture, RTL, and circuit design.
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ASIC RTL Design Engineer (Sr. Engr / Sr. Lead Engr) QualcommBangalore, India 14d Designing system power management IP cores and subsystems for Snapdragon SoCs used in mobile, compute, IoT, and automotive markets.
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E-core CPU Design Manager IntelMalaysia, Penang 14d Manage a high-performing team responsible for the physical design of high-performance Intel E-core microprocessors from synthesis through post-layout verification and tapeout.
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Senior CPU Power Architect NVIDIAUS, CA, Santa Clara $152k–$242k14d Drive and optimize CPU power efficiency across the design cycle from architectural modeling to silicon validation to achieve aggressive performance-per-watt goals.
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Technical Director - FE NxpNoida, IN 14d Define U-arch from high-level specs and lead hands-on design, architecture, and integration of System on Chip (SoC) from specification to tapeout.
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Staff Engineer Design InfineonBangalore BTP 14d Develop and implement innovative digital design flows for SoC synthesis, equivalence checking, and physical design to ensure efficient timing closure and physical sign-off.
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Senior ASIC Modelling Engineer↗ European Tech RecruitCork, County Cork, Ireland 14d Develop memory subsystems and client IP modelling for next-generation advanced SoCs, focusing on coherency protocols, NoC interconnect fabrics, system cache, and memory controllers.
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GPU Hardware Datapath Design Engineer↗ Imagination TechnologiesKings Langley, England, UK 14d Design optimal arithmetic hardware components and research new techniques for implementing mathematical operations in silicon for high-performance GPU products.
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Physical Design Engineer, New Grad SambanovasystemsAustin, TX $120k–$150k14d Run and improve RTL to GDS flow on advanced process nodes for RDU chip designs.
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Chip Lead Advanced Micro Devices, IncSanta Clara, California 14d Lead chip development from architecture through production, partnering with cross-functional teams to deliver silicon products.
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Principal Digital Design Engineer - MCU NXP SemiconductorsCatania, Provincia di Catania €61k14d Lead full digital IC design flow for complex System-on-Chip (SOC) including specification, architectural design, RTL coding, synthesis, verification, and power analysis for high-performance MCUs.
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Synthesis & STA Engineer – High-Speed SerDes AsteralabsSan Jose $160k–$200k14d Drive logic synthesis and static timing analysis (STA) for digital controller and DSP blocks within high-speed analog/mixed-signal SerDes PHY designs.
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SoC Top RTL Integration Engineer↗ SemidynamicsBarcelona, CT, ES 15d Integrate multiple subsystems (CPU clusters, memory, accelerators, peripherals) into the top-level RTL of high-performance SoCs, connecting them via interconnects and NoCs to prepare designs for tape-out.
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IC Physical Design Engineer↗ PersolClementi, S00, SG 15d IC physical design of 12nm/6nm/4nm and below advanced process chips, handling tasks from RTL to GDS.
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SoC Design Engineer↗ Microchip TechnologyBurnaby, BC, CA $86k–$186k15d Define advanced technical direction, architectures, methodologies, and reusable solutions for semiconductor architecture, RTL, and circuit design.
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Engineer - Physical design ArmBengaluru, India 15d Physical design engineer specializing in RTL-to-GDSII flow for next-generation SoC projects, focusing on synthesis, placement, CTS, routing, and timing closure.
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PRINCIPAL ENGINEER, ASIC DESIGN MicronHyderabad, Telangana, India 15d Drive IP, Subsystem, and SoC development for next-generation memory and storage products, owning design from micro-architecture through RTL compose, integration, and physical hardware assistance.
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ASIC Power Engineer AppleSan Diego, United States of America 15d Define low-power architecture, perform power modeling, analysis, and silicon validation for wireless communication SoCs.
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Staff Engineer - DFT MarvellBangalore, IN 15d Design, implement, and verify Digital Design for Test (DFT) and Static Timing Analysis (STA) flows for networking SoCs spanning copper and optical products.
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Lead Product Engineer CadenceBANGALORE, IN 15d Lead timing signoff and ECO for advanced System-on-Chips (SoCs) using industry-standard tools, driving timing closure and supporting technology node bring-up.
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Senior VLSI ASIC Logic Design Engineer HpeFt. Collins, Colorado, United States of America $147k–$279k15d Designs, analyzes, develops, modifies, and evaluates VLSI components and hardware systems, determining architecture and logic design while building physical implementations of complex integrated circuits.
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FPGA Design Engineer, Senior↗ Positron AIRemote $200k–$250k15d Design, implement, and validate FPGA and ASIC networking functions and digital logic for low-latency, high-throughput large language model inference accelerators.
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Senior Physical Design Engineer↗ Capgemini EngineeringCT, ES 15d Drive physical design activities across the implementation flow from floorplanning through sign-off and tape-out for complex designs on advanced technology nodes.
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