ASIC Physical Design
1,421 open positions
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Sr Principal Engineer- Switch Architecture MarvellBangalore 24d Define architecture for next-generation Teralynx data center switch ASICs, driving product definition from concept to silicon.
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Director, ASIC Software Engineering BlueoriginKraków, Poland 24d Lead a multidisciplinary software organization to develop the full software ecosystem for custom ASICs and SoCs, enabling next-generation space-based communications for Terawave systems.
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STA Physical Design Engineer, Senior Principal AsteralabsSan Jose $207k–$207k24d Senior Principal Physical Design Engineer driving planning, coordination, and execution for connectivity ASIC design from RTL to GDS for leading cloud service providers and OEMs.
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Staff Engineer, Physical Design Renesas-ElectronicsBengaluru, KA, in 25d Lead subsystem- and block-level physical implementation and closure for complex hierarchical SoCs at advanced technology nodes, focusing on timing, congestion, power integrity, and clocking methodologies.
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Senior Silicon Logical Design Engineer - Bengaluru GraphcoreBengaluru 25d Designing microarchitecture and RTL for Graphcore AI chips, integrating IP and subsystems into top-level SoC designs.
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Lead Product Engineer CadenceBANGALORE 25d Lead Product Engineer for Genus Synthesis Solution, a logic synthesis software that converts high-level language designs into logic gates to optimize Power, Performance, and Area (PPA) for digital ASICs.
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Senior Manager, Digital Design Engineering AnalogdevicesChina, Shanghai, Pudong, ZuChongzhi 25d Lead digital IC development for cutting-edge optical control ICs in AI data center and cloud infrastructure applications, guiding teams from architecture definition through tape-out.
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Physical Design, VLSI - New College Grad 2027 NVIDIAChina, Shanghai 25d Physical Design Engineer for NVIDIA GPU and Mobile chips, handling full chip floorplanning, place & route, timing closure, and power/signal integrity analysis.
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FPGA IP Software Engineering Manager AlteraPenang 15, Penang, Malaysia 25d Architect FPGA IPs (ORAN, eCPRI, CPRI) for 5G and next-gen terrestrial/non-terrestrial networks.
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Compiler Circuit Designer↗ AppleSanta Clara, CA, US $176k–$176k25d Design SRAM, register files, and latch arrays for high-performance, low-power ASICs and processors.
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DFT Design Engineer, Machine Learning Acceleration
AmazonAustin, Texas, United States
$136k–$184k25d
Design and optimize hardware for AWS custom machine learning inference and training servers (Inferentia and Trainium) by developing advanced Design for Test (DFT) architectures.
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ASIC Design Engineer, Sr. Staff-18490↗ SynopsysRemote $138k–$138k25d Design, develop, and maintain PHYINIT configuration software and runtime firmware for Synopsys DDR PHY IP, enabling high-speed memory interfaces in customer silicon.
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Design Engineer - STA BroadcomUSA-Colorado-Fort Collins-4380 Ziegler Road $110k–$110k25d Chip-level timing architecture, analysis, and closure for advanced ASICs in deep sub-micron technologies (3nm and smaller) for AI, computing, and networking SoCs.
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Electronics Engineer - HDL Universal-QuantumHaywards Heath, England, United Kingdom 26d Design and realize HDL systems for control systems in quantum computers.
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Digital IC Design Engineer | Sensing PS Texas InstrumentsDallas, TX, United States 26d Develop digital IP and RTL implementation for sensing IC solutions (magnetic, inductive, current) combining with analog technology.
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Senior FPGA & Imaging Systems Engineer ON SemiconductorRaleigh, NC, United States 26d Design and develop high-speed digital hardware and FPGA-based solutions for next-generation Short-Wave Infrared (SWIR) imaging systems used in industrial, scientific, aerospace, and machine vision applications.
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SOC chip lead NxpPune 26d Own end-to-end SoC program execution from project definition through tape-out and post-silicon support, ensuring on-time, high-quality delivery of key milestones.
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CPU Cores Global Performance Lead↗ AMDAustin, TX, US 26d Lead a distributed team to drive end-to-end performance analysis and optimization for AMD's next-generation CPU cores.
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Physical Design for PPA Optimization Engineer IntelIsrael, Haifa 26d Optimizing Intel's process technology and physical design flows to achieve best-in-class Power, Performance, and Area (PPA) for IPs.
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Member of the Technical Staff, IP Engineering GlobalFoundriesHsinchu 27d Develop high-performance computing processor IP products and drive technical planning for product development and customer engagements.
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Power Infrastructure Engineer SifiveSanta Clara, California, United States $206k–$206k27d Develop and deploy methodology and infrastructure to measure, analyze, and model power consumption for SiFive IP.
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Embedded Software Engineer (FPGA)↗ Dl RemoteRemote $100k–$100k27d Designing and implementing complex FPGA architectures and RTL logic for high-speed data processing systems, leading hardware-software integration.
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Senior Hardware Design Engineer, High Speed Networking Arista-NetworksNashua, NH, us 28d Design and develop high-speed networking and Ethernet products for enterprise campuses, hyperscale datacenters, and AI clusters.
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Principal Memory Subsystem Engineer (Design or DV) MicrosoftUnited States, California, Mountain View 29d Provide technical leadership for high-performance Memory Subsystem development, driving solutions from architecture through silicon bring-up for complex SoCs.
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Hardware Engineer Nexthop Systems IncSydney, New South Wales 29d Design and develop Ethernet switches, CPU subsystems, memory, and networking interfaces for datacenter AI infrastructure.
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Sr. Staff SoC Power & Performance Architect AmbiqmicroincAustin HQ 29d Architecting power and performance for low-power System-on-Chips (SoCs) from early design through silicon validation.
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Sr. Staff PCB Design Engineer d-MatrixSanta Clara 29d Lead physical design of high-complexity AI accelerator boards (20+ layers) ensuring clean 112G/224G SerDes signals and robust power delivery for AI silicon.
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Layout/Mask Designer Otsi GlobalFolsom, California, United States 29d Develops and implements physical design solutions for System-on-Chip (SoC) devices from RTL, netlists, and design constraints.
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SSD Hardware Architect MicronLongmont, Colorado, United States of America $152k–$152k1mo Design next-generation Solid State Drive (SSD) hardware architectures, power topologies, and system-level performance solutions.
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ASIC Synthesis and STA Engineer - New Grad CienaOttawa $71k–$71k1mo Execute frontend implementation for ASIC IP subsystems, focusing on synthesis, static timing analysis, logical equivalence checking, and clock domain crossing validation.
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Staff Engineer, Static Timing Analysis CAD Engineer Samsung Electronics3900 N Capital of Texas Hwy, Austin, TX, USA $151k–$151k1mo Ensuring timing integrity and signoff readiness for next-generation GPU IPs used in premium smartphones and high-performance computing devices.
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