Staff / Principal ASIC Design Engineer
Core
Designing digital blocks for high-performance AI infrastructure connectivity chips (CXL, Ethernet, NVLink, PCIe, UALink) in deep-submicron processes.
Role type
Staff / Principal ASIC Design Engineer (Digital)
Builds
Custom connectivity solutions and standards-based AI infrastructure components
Domain
Semiconductor / AI Infrastructure / High-Speed Connectivity
Required skills
Verilog, SystemVerilog, RTL coding, Micro-architecture, EDA tools (Lint, CDC, Synthesis, Timing, Power), PPA optimization, Debugging, Clock Domain Crossing
Preferred skills
DDR and PCIe protocols, Power management techniques, Python or Perl scripting, High-speed serial interface designs
Technologies
CXL, Ethernet, NVLink, PCIe, UALink, RTL, EDA tools
Responsibilities
Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support; Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions; Serve as the point of contact for logic blocks interacting with Architecture, Verification, and Backend teams; Utilize industry-leading EDA tools to ensure designs are robust, scalable, and power-efficient; Contribute to design quality through verification and validation activities; Participate in design methodology improvements and tool automation initiatives
Seniority
Staff / Principal, hands-on IC
