Lead Product Engineer
Core
Lead Product Engineer performing static timing analysis, timing closure, and ECO for advanced SoCs using industry-standard tools.
Role type
Senior IC physical design engineer (timing signoff)
Builds
Advanced semiconductor chips (SoCs) for consumer, hyperscale computing, 5G, automotive, aerospace, and health applications
Domain
Semiconductor / Electronic Design Automation (EDA)
Required skills
Static timing analysis (STA), Timing closure, PrimeTime, Tempus, MMMC scenarios, OCV/AOCV/SOCV, LVF, Python scripting, Tcl scripting
Preferred skills
SPICE simulation and correlation, Debugging large SoC environments, Advanced node bring-up (5nm/3nm/2nm), AI/LLM concepts, CLI-based infrastructure automation
Technologies
PrimeTime, Tempus, Python, Tcl, SPICE
Responsibilities
Perform static timing analysis across MMMC scenarios, Debug setup/hold violations and variation-related issues, Drive timing closure using PBA/GBA and derating techniques, Implement physical-aware timing ECOs, Perform STA vs SPICE correlation, Support foundry enablement and technology node bring-up, Develop automation for timing workflows
Seniority
Senior, hands-on IC
