Director of Physical Design
Core
Lead and scale the physical implementation organization for next-generation ultra-low-power microcontroller (MCU) products, driving the physical design roadmap to ensure world-class PPA (power, performance, area) and deliver robust silicon for high-volume embedded applications.
Role type
Director of Physical Design
Builds
Ultra-low-power microcontroller (MCU) SoCs
Domain
Semiconductor / Low-power embedded systems
Required skills
Low power design techniques (UPF, clock gating, multi-Vt, power gating, DVFS, retention), Physical design tools (Synopsys, Cadence, Mentor), Advanced process nodes (40nm to 12nm and below), MCU architecture expertise, Floorplanning, Power planning, Clock tree synthesis (CTS), Place & route (P&R), Timing closure, Physical verification (DRC/LVS), EM/IR analysis, Tape-out readiness management
Preferred skills
Mixed-signal SoC integration, High-volume consumer/industrial MCU background, Security-focused or safety-certified design experience (ISO 26262), Scaling distributed engineering teams
Technologies
Synopsys, Cadence, Mentor, UPF, DVFS, DRC, LVS
Responsibilities
Define and execute physical design strategy for low-power MCU product lines, Build and mentor a high-performing global physical design team, Establish best-in-class methodologies for low-power physical implementation, Oversee full-chip and block-level physical design including floorplanning, CTS, P&R, and timing closure, Partner with architecture, RTL, and analog teams to influence early design decisions, Own physical design schedules, resource planning, and risk management
Seniority
Director, strategic leadership with hands-on technical oversight
