ASIC Physical Design

2,682 open positions

架构和性能分析工程师-Data（上海） ByteDance上海 Design SoC system architecture (SoC/CPU architecture and microarchitecture definition) and optimize server system performance and power consumption based on models.
芯片系统架构师-PICO ByteDance北京 Define MR product SOC architecture requirements, internal data path control, and hardware/software partitioning to optimize performance, power, and area.
资深芯片软件系统分析师（稳定性和可管理性方向）-Data ByteDance北京 Design and deliver stability solutions for chip products in data center scenarios, optimizing software/hardware architectures to ensure reliability in critical business chains.
ESD专家（存算与AI） - 芯片研发 ByteDance北京 Design and validate ESD architecture, models, and strategies for monolithic storage-computing AI chips to ensure reliability in high-efficiency computing applications.
SoC系统软件架构师/工程师 - 芯片研发 ByteDance北京 Design and optimize system software architecture for self-developed SoC chips, supporting large-scale deployment in data centers and solving critical online issues.
芯片综合/STA工程师（存算与AI） - 芯片研发 ByteDance北京 Synthesize RTL, perform formal verification, power checks, and sign-off for SoC chips targeting AI large model applications to break memory wall bottlenecks.
Senior SoC Digital Design Engineer, Multimedia Lab TikTokSan Jose, United States of America Design hardware accelerators for advanced video encoding and processing within scalable video codec solutions (FPGA and ASIC).
SOC架构工程师（存算与AI） - 芯片研发 ByteDance北京 Design high-efficiency AI chips based on in-memory computing architecture to break the 'memory wall' bottleneck and provide high-performance computing for AI large models.
SoC设计工程师（上海） - 芯片研发 ByteDance上海 Designing custom hardware optimization for ByteDance's business scenarios, including defining specs, SoC integration, IP selection, and RTL design for advanced semiconductor process cloud chips.
Technical Program Manager, Silicon Physical Design MatXMountain View $120k–$600k Own cross-functional execution of advanced System-on-Chip (SoC) programs from early planning through tapeout for high-performance AI silicon.
系统架构工程师（存算与AI） - 芯片研发 ByteDance北京 Design high-efficiency AI chips based on in-memory computing architecture to break the 'memory wall' bottleneck and provide a high-efficiency computing foundation for AI large models.
芯片设计工程师 TencentShanghai, China Design, implement, and optimize digital chips, supporting verification and backend teams.
芯片设计工程师(北京/上海/深圳) TencentShenzhen, China Design and implement SoC/IP systems and subsystems, focusing on module architecture, RTL implementation, timing analysis, and PPA optimization.
芯片设计工程师(北京/上海/深圳) TencentShanghai, China Design and implement SoC/IP systems and subsystems, focusing on module architecture, RTL implementation, timing analysis, and PPA optimization.
芯片架构师(北京/深圳) TencentShenzhen, China Designing and optimizing SoC architecture, including bus topology, QoS strategies, address translation, memory access behavior, and IO device-CPU cache consistency.
硬件开发-AI核设计方向(北京/上海/深圳) TencentShanghai, China Design AI core microarchitecture, RTL implementation, timing analysis, and PPA optimization.
硬件开发-AI核设计方向(北京/上海/深圳) TencentShenzhen, China Designing AI core microarchitecture, RTL implementation, timing analysis, and PPA optimization for AI chips.
芯片性能架构师-服务器 ByteDance深圳 Design and optimize server chip architectures for data center applications, focusing on performance, power, and area (PPA) efficiency through software-defined architecture and workload analysis.
交换机硬件工程师-基础设施 ByteDance北京 Design, debug, and mass-produce data center switch CPU chips and subsystems (BMC, BIOS, SSD, DDR) while ensuring circuit design metrics, reliability, and consistency.
DTCO负责人（存算与AI） - 芯片研发 ByteDance北京 Design high-efficiency AI chips based on in-memory computing architecture to break the 'memory wall' bottleneck and provide a high-efficiency computing foundation for AI large models.
SoC Digital Design Engineer, Multimedia Lab TikTokSan Jose, United States of America Design hardware accelerators for advanced video encoding and processing within scalable video codec solutions.
芯片后端设计工程师（芯片平台） - 芯片研发 ByteDance北京 End-to-end backend design for CPU/ASIC chips from Netlist to GDSII, including signoff (APR, PV, STA, IR) and supporting tape-out, packaging, and mass production.
AI存储固件开发工程师（前端/存算与AI） - 芯片研发 ByteDance北京 Design custom NAND product front-end systems and storage/compute front-end modules for storage-in-compute AI chips to optimize performance and reliability for inference scenarios.
数字设计负责人（存算与AI） - 芯片研发 ByteDance北京 Lead the design and management of high-efficiency AI chips based on in-memory computing architecture to break the 'memory wall' bottleneck and provide a high-efficiency computing base for AI business.
Director of Analog Design – Wearable SoCs (On-site. West Lafayette, USA) IxanaWest Lafayette, IN $175k Architect next-generation Wi-R SoCs integrating analog/RF front-end, ultra-low-power digital blocks, and sensor interfaces for brain-inspired wearable computing.
混合信号/高速接口ASIC设计工程师（芯片平台） - 芯片研发 ByteDance北京 Design high-speed interface IP for silicon front-end, covering architecture modeling, RTL implementation, and post-silicon test analysis.
系统架构工程师（低功耗方向/存算与AI） - 芯片研发 ByteDance北京 Design high-efficiency AI chips based on in-memory computing architecture to break the 'memory wall' bottleneck and provide a high-efficiency computing base for AI large models.
数字设计专家-PICO ByteDance上海 Lead digital design for custom image sensors in AR/VR products, defining block-level specs, RTL design, and integration.
芯片建模工程师（存算与AI） - 芯片研发 ByteDance北京 Develop high-efficiency AI chips based on in-memory computing architectures to address the 'memory wall' bottleneck and support large AI model applications.
芯片综合/STA工程师（芯片平台） - 芯片研发 ByteDance北京 Perform logic synthesis, formal verification, and STA signoff for SoC chips, collaborating on clock/reset, low power, and timing convergence strategies.
系统开发工程师（存算与AI） - 芯片研发 ByteDance上海 Design high-efficiency AI chips based on in-memory computing architecture to break the 'memory wall' bottleneck and provide a high-efficiency computing base for AI large models.
数字后端设计工程师（存算与AI） - 芯片研发 ByteDance北京 Design high-efficiency AI chips based on in-memory computing architecture to break the 'memory wall' bottleneck and serve AI large model applications.

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