ASIC Design - Floorplan Engineer
Core
Define and optimize top-level floorplan architecture, macro placement, power grid, and clock distribution for advanced CMOS ASICs operating at speeds exceeding 1 GHz.
Role type
Senior IC ASIC Floorplan Engineer
Builds
Custom CMOS ASICs for AI, Cellular, Networking, Computing, and Storage products
Domain
Semiconductor / VLSI Physical Design
Required skills
VLSI design principles, floorplanning, die partitioning, hierarchical design, macro placement, power grid design, clock distribution, PPA optimization, TCL scripting, Linux environments
Preferred skills
Python, Perl, Ruby, Cadence physical design tools, block PnR, timing closure, physical verification, IR/EM analysis
Technologies
3 nm process nodes, Cadence, TCL, Linux
Responsibilities
Define and optimize top-level floorplan architecture including die size estimation and hierarchy; Drive macro placement, power grid design, clock distribution planning, and pin placement; Collaborate with RTL, timing, and packaging teams to balance PPA targets; Lead top-level timing closure, congestion analysis, and ECO implementation; Coordinate with block owners for integration convergence; Contribute to design flow automation and methodology development.
Seniority
Senior, hands-on IC with technical leadership
