Principal Physical Design Engineer
Core
Lead physical design implementation for next-generation high-performance networking, AI/ML accelerators, and custom cloud ASICs, transforming ultra-complex architectures into high-yielding silicon.
Role type
Principal Physical Design Engineer (IC)
Builds
Custom ASICs for hyper-scale cloud providers, AI pioneers, and tier-1 networking infrastructure leaders
Domain
Semiconductor / ASIC Physical Design
Deliverable
production ML models
Required skills
Block-level and top-level floorplanning, Synthesis, Place and Route (P&R), Clock Tree Synthesis (CTS), Timing Closure, Signoff, Multi-corner multi-mode (MCMM) Static Timing Analysis (STA), Signal Integrity (SI) optimization, Power Grid Optimization, TCL scripting, Python scripting, Unix shell scripting
Preferred skills
High-speed clock network implementation (H-tree, mesh), Power-aware implementation flows (UPF/CPF, multi-voltage domains, clock/power gating)
Technologies
Cadence Innovus, Synopsys PrimeTime, Cadence Tempus, StarRC, QRC, RedHawk, Siemens Calibre
Responsibilities
Lead block-level and top-level implementation from floorplanning to GDSII stream-out, Drive floorplanning, placement, CTS, routing, and timing/power optimization on advanced technology nodes (5nm, 3nm, 2nm), Perform multi-corner multi-mode (MCMM) static timing analysis (STA), signal integrity (SI) optimization, and power grid optimization for signoff
Seniority
Principal, hands-on IC
