ASIC Physical Design
2,687 open positions
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Solutions Architect-FPGA Advanced Micro Devices, IncSan Jose, California 12d Architect and develop hardware/software co-design solutions for FPGA-based acceleration in networking, storage, automotive, aerospace, and AI/ML workloads.
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Principal FPGA Emulation Engineer Renesas-ElectronicsAustin, TX, us 12d Build and own FPGA-based platforms to emulate mixed-signal power ASICs before silicon, validating real-time digital, mixed-signal, and power-control architectures.
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SiP System and Design Architect (m/f/d) AumovioRegensburg, BY, de 12d Translating product requirements into executable SiP functional architectures, chip/chiplet partitions, and package-level design concepts for automotive electronics.
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Staff Engineer, Digital Design Engineering Analog DevicesEspaña 12d Design complex mixed-signal integrated circuits for automotive high-speed serial data communications (GMSL SerDes) for safety and infotainment systems.
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Physical Design Engineer QualcommSanta Clara, California, United States of America 13d Execute and drive all stages of the physical design flow from synthesized netlist to tape-out for complex, high-speed, and low-power ASICs and SoCs.
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Staff Hardware Engineer ArmCambridge, United Kingdom 13d Design, develop, and verify synthesizable RTL for innovative hardware platforms and subsystems, balancing performance, power, and area.
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Lead Product Engineer - Synthesis Siemens-EdaBangalore, IND, India 13d Lead a team of engineers to solve critical logic synthesis challenges and drive the roadmap for next-generation RTL2GDSII solutions for complex digital IC designs.
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Graphics (GPU) RTL Design Engineer AppleAustin, United States of America 13d Design and manufacture high-performance, power-efficient GPU microarchitectures for mobile and PC devices.
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Principal Modem SOC Design Engineer - Terawave BlueoriginCentral Texas, US $269k–$377k13d Technical design leader for the TeraWave satellite communication System on Chip (SOC), leading RTL design and microarchitecture definition for modem subsystems.
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Staff Digital Design Engineer InfineonSan Jose, CA 13d Execute hands-on digital IP and SoC design, including micro-architecture refinement, RTL implementation, and integration support for automotive networking chips.
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ASIC Engineer CiscoBangalore, India 13d Define, design, and verify high-performance ASIC and ASIC subsystems for deployment in Cisco networking platforms.
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Principal ASIC Engineering Program Manager HpeFt. Collins, Colorado, United States of America $140k–$321k13d Provide strategic technical coordination and program leadership for complex ASIC development across architecture, design, verification, physical implementation, validation, and manufacturing readiness.
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SiP System and Design Architect (m/f/d) AUMOVIO SE HaupverwaltungDeutschland 13d Translating product requirements into executable SiP functional architectures, chip/chiplet partitions, and package-level design concepts for automotive electronics.
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Senior Principal Engineer, Physical Designer MarvellSanta Clara, CA, US $178k–$266k13d Senior leader shaping long-term vision and leading RTL-to-GDSII implementation for next-generation high-performance processor chips in leading-edge CMOS processes for server and networking applications.
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CPU Physical Design Engineer IntelUS, Texas, Austin $106k–$200k13d Physical design and verification of high-performance, power-efficient CPUs from RTL to GDSII.
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Junior ASIC Backend Engineer AxisSweden - Lund 13d Implementing the physical design phase of ARTPEC SoC chips, including floor-planning, synthesis, timing closure, and power integrity analysis.
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Digital Design Manager GlobalFoundriesITA - Lombardy - Pavia, IT 13d Lead the development of digital architecture and implementation for next-generation power management ASICs, specifically high-performance DC-DC converter solutions for AI and data center applications.
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Staff Engineer, ASIC Digital Design MicronMinneapolis, Minnesota, United States of America $150k–$256k13d Design next-generation DRAM/NAND/SSD controllers and systems, translating architectural requirements into detailed microarchitecture specifications and robust hardware implementations.
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Senior FPGA Research Engineer↗ BarcoVancouver, BC, CA 13d Lead FPGA architecture for sensor acquisition, synchronization, aggregation, and delivery to edge AI compute modules in industrial imaging systems.
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Senior FPGA Engineer (Hybrid)↗ Kardium Inc.Burnaby, BC, CA CA$100k–CA$150k13d Develop and verify FPGA-based systems for a medical device treating atrial fibrillation.
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Power Methodology and Analysis Engineer NVIDIAChina, Shanghai 13d Researching, developing, and deploying methodologies to analyze and reduce power consumption of NVIDIA chips, specifically GPUs and Tegra SOCs.
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Senior Logic Design Engineer MicrosoftUnited States, Oregon, Hillsboro 13d Design and build PCIe subsystems and other IP blocks for System-on-Chip (SoC) implementations, ensuring they meet area, power, and performance requirements.
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SoC Clocking Specialist (Physical Design) Enchargeai36India 13d Lead clock architecture and physical implementation for next-generation edge AI hardware SoCs.
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FPGA Design Engineer - 1091 QuantinuumUS Broomfield, CO 13d Lead FPGA design for the digital control system of Apollo quantum computers, coordinating electronics and interfacing with DACs/ADCs, DDRx memory, and signal processing.
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Physical ASIC Design Implementation Engineer EngibexLeuven 13d Physical Implementation engineer for full backend (P&R) projects from netlist-in to GDSII-out flow, handling toplevel chips and blocklevel blocks.
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