ASIC Physical Design
1,420 open positions
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Physical Design Engineer/STA AlteraRegus, Madhapur 19d Performs physical design implementation of custom IP and SoC designs from RTL to GDS, conducting verification and signoff to create manufacturing-ready design databases.
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Design Engineer↗ ArmKA, IN 19d Develop transistor-level physical layouts for Arm custom standard cells in sub-3nm process nodes to deliver high-performance, area-optimized logic libraries for next-generation SoCs and custom digital IPs.
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Digital Design Engineer - MCU NxpCatania $38k–$38k19d Develop digital sub-circuits for complex System-on-Chip (SoC) designs, focusing on RTL coding, synthesis, verification, and power analysis for high-performance microcontrollers.
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Staff Silicon Physical Design Engineer - Bengaluru GraphcoreBengaluru 21d Designing high-performance, power-efficient AI superchips at leading-edge process nodes using state-of-the-art EDA tools and in-house flows.
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FPGA Design Engineer - 964 QuantinuumUS Broomfield, CO 21d Lead FPGA design for the digital control system of quantum computers, coordinating electronics and processing signals.
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FPGA Designer↗ Lumentum OperationsOttawa, ON, CA $93k–$93k21d Design control and datapath logic for next-generation optical cloud and networking technology using FPGAs.
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FPGA Design Engineer↗ Aten Canada Technologies Inc.Richmond, BC, CA $60k–$60k21d Develop and verify high-speed FPGA systems and implement data/signal processing algorithms for world-leading KVM switches.
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?SoC-FPGA Entwickler (m/w/d) Backnang, BADEN_WUERTTEMBERG 21d Design, verification, and deployment of complex FPGA/SoC solutions for high-tech industrial manufacturing systems.
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Principal Design Engineer MicrosoftUnited States, California, Mountain View 21d Leading high-performance, high-bandwidth digital design for IP microarchitecture, RTL, synthesis, and SoC integration.
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Principal Electrical Design Engineer AsteralabsSan Jose 22d Define and drive architecture, design, and technical strategy for advanced board-level hardware across next-generation networking and high-performance connectivity platforms.
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SRAM Physical Design Engineer↗ AMDBoxborough, MA, US 22d Design and optimize high-performance SRAM and memory structures for next-generation CPU cores.
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Physical Design Engineer MarvellCordoba, Argentina 22d Physical design and methodology for next-generation high-performance processor chips in leading-edge CMOS process technology.
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Senior ASIC Engineer, Switch SoC NVIDIAIndia, Bengaluru 22d Design and integrate next-generation Switch Silicon chips, defining system-level methodologies and driving cross-functional teams to deliver high-throughput, low-latency communication devices.
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Sr HW Design Engineer FfiveSpokane Valley, US $161k–$161k22d Lead system-level hardware design for high-performance electronic systems, driving development from concept through production release.
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Physical Design Engineer↗ Marvell TechnologyCórdoba, X, AR 22d Physical design and methodology for next-generation high-performance processor chips in leading-edge CMOS process technology.
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FPGA Designer LumentumCanada - Ottawa (Bill Leathem) $93k–$93k22d Design control and datapath logic for advanced photonic modules powering AI, cloud computing, and telecom networks.
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Researchers (Secure FPGA Design and Verification)↗ Tum Create LimitedClementi, S00, SG 22d Developing an open and verifiable Quantum safe RISC-V processor platform for post-quantum security research.
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Semiconductor Design Engineer MicronSan Jose, CA $174k–$174k22d Design and validate on-chip controllers and mixed-signal circuitry for NAND Flash chips, including architecture development, system integration, and full-chip validation.
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?Senior Softwareingenieur FPGA / VHDL (m/w/d) Ulm, Donau, BADEN_WUERTTEMBERG 22d Develop and implement FPGA and VHDL-based solutions and FPGA firmware for embedded systems.
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Digital Design Engineer SilabsOslo $479k–$479k22d Develop digital architectures, IP, processors, compute engines, and peripherals for Silicon Labs IoT mixed-signal SoCs.
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Sr. Director, SoC Architecture AmbiqmicroincAustin HQ 23d Define system architecture for next-generation ultra-low-power AI SoCs powering wearables, IoT, and battery-constrained edge devices.
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Senior Engineer, Physical Design - Interconnects SifiveBengaluru, Karnataka, India 23d Senior Physical Design Engineer responsible for RTL-to-GDSII implementation of high-speed System IP components including Network-on-Chips (NoC), coherent CPU clusters, and Uncore subsystems.
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Neuromorphic Front-End Silicon Lead IntelUS, Oregon, Hillsboro $221k–$312k23d Lead design and verification of neuromorphic chiplets and IP for physical AI systems, translating hardware innovations into manufacturable silicon.
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Digital Hardware Engineer↗ QualcommSan Diego, CA, US $90k–$90k23d Develop and verify complex wireless systems, specifically a Test Base Station (TBS) for 6G physical layer functionality.
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Digital Design Engineer Lead - Custom Silicon Management↗ AppleAustin, TX, US $176k–$176k23d Lead technical engagements between Apple and silicon suppliers to define, develop, and productize custom silicon for mobile products including iPhone, iPad, and AppleTV.
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Power Engineering Architect CerebrasSunnyvale, CA $230k–$230k23d Lead power delivery architecture and strategy for high-performance compute, AI/ML accelerators, and advanced ASIC platforms.
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Senior Physical Design Engineer - P&R↗ Bta Design ServicesRemote 23d Senior Physical Design Engineer owning backend implementation from netlist to GDSII for advanced silicon platforms targeting next-gen AI infrastructure.
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?FPGA und Embedded Software Ingenieur (m/w/d) Remote 23d Design and verification of FPGA modules for Xilinx SoCs, development of C++ drivers, and embedded signal processing software in C++ (RTOS).
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ASIC Development Engineer↗ Microchip TechnologyBurnaby, BC, CA $76k–$76k23d Design, verification, emulation, and validation of digital integrated circuits (SoCs) for storage and memory controllers.
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Leader, Hardware Engineering - 10+ years of proven experience as Product/Design Engineer with expertise in electronic product design and architecture. CiscoBangalore, India 23d Lead a product engineering team delivering high-performance routers and switches (Cisco 8000 series) using Silicon One ASIC architecture for AI and 5G networks.
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System IP RTL Design Lead TenstorrentBengaluru 23d Lead the definition, selection, and integration of complex datacenter-class System IP and SoC architectures for next-generation semiconductor products.
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ASIC Engineering Director BlueoriginKraków, Poland 24d Establish and lead the ASIC engineering organization in Krakow, Poland, focusing on design verification, front-end design, digital architecture, and embedded hardware integration for high-performance communication SoCs.
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