Staff Physical Design Engineer - SoC EMIR Engineer
Core
Backend power methodologies and EMIR analysis for high-performance SoCs enabling AI clusters.
Role type
Staff Physical Design Engineer (SoC EMIR)
Builds
High-performance connectivity silicon for AI and cloud environments
Domain
Semiconductor / AI Infrastructure
Deliverable
production ML models
Required skills
EMIR analysis, IR drop analysis, signal/power electromigration, Ansys RedHawk, Cadence Voltus, FinFET node expertise, Place & Route flows, power grid synthesis, root-cause analysis
Preferred skills
Thermal analysis, sign-off criteria, timing, packaging, TCL scripting
Technologies
Ansys RedHawk, Cadence Voltus, FinFET, TCL
Responsibilities
Perform IR drop and signal/power electromigration analysis on complex chips, collaborate with Physical Design team for power integrity, partner with Package Design engineers for Chip-Package co-analysis, analyze root causes for voltage drop violations and EM risks
Seniority
Staff, hands-on IC
