Copy of Staff/ Principal Chip Top Physical Design Engineer
Core
Execute SoC Top-level physical design and full-chip convergence for chips driving the world's largest AI clusters.
Role type
Staff/Principal Chip Top Physical Design Engineer
Builds
Custom connectivity solutions for rack-scale AI infrastructure
Domain
Semiconductor / AI Infrastructure / Deep-submicron processes
Deliverable
production ML models
Required skills
SoC Top-level physical design, Floor-planning, Place & Route (P&R), Clock Tree Synthesis (CTS), Power/Clock distribution, Power Integrity, Timing signoff, Physical Verification (DRC/LVS), Formal Verification, Low-power implementation (UPF/CPF), EMIR, RTL2GDS flows, Advanced process technologies (5nm, 3nm), Macro/subsystem-level designs, Full-Chip integration, EDA tools (Synopsys Fusion Compiler/ICC2, Cadence Innovus)
Preferred skills
Power & Noise analysis (EM/IR), DFT integration, High-speed interfaces, Data center protocols
Technologies
Synopsys Fusion Compiler, ICC2, Cadence Innovus, UPF, CPF, EMIR, DRC, LVS, CTS, P&R
Responsibilities
Execute SoC Top-level physical design and drive full-chip convergence; Perform floor-planning, P&R, CTS, power/clock distribution, and signoff; Collaborate with Architecture, Design, DFT, and Product teams to optimize PPA; Resolve signal integrity, thermal, and power challenges; Collaborate with Package team on Bump-map-to-Ballout design.
Seniority
Staff/Principal, hands-on IC
