ASIC Physical Design
1,415 open positions
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Physical Design Implementation and Signoff Methodology Lead & Architect AlteraSan Jose, California, United States $232k–$232k5d Architect and own the end-to-end physical design implementation and signoff methodology (place-and-route, EMIR, timing, power) across Altera's FPGA product portfolio, integrating AI/ML techniques to improve closure speed and quality.
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Senior FPGA Engineer RebuildmanufacturingRe:Build AppliedLogix $125k–$125k7d Senior FPGA engineer architecting and implementing robust RTL designs for diverse client applications in embedded systems, from initial concept through lab debug.
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RTL Intern EtchedSan Jose 8d Design microarchitecture and implement logic in Verilog for cutting-edge machine learning architectures.
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Processor Core Logic Design/Architect CadenceAUSTIN 8d Architect and design enhancements to processor core logic, partnering with the Chief Architect to identify and solve performance opportunities.
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Director, Digital Design AnalogdevicesIndia, Bangalore, RMZ 8d Lead digital design activities and provide technical leadership for silicon development across one or more products.
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Senior Chip Design Engineer NVIDIAIsrael, Beer Sheva 8d Design and implement next-generation Networking Silicon chips, focusing on core units, micro-architecture, and RTL implementation to deliver high-throughput, low-latency communication devices.
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Next Gen CPU Power Management RTL Design Engineer↗ AMDSanta Clara, CA, US 8d Design core clocking, reset, and power management IP for next-generation AMD processors (Ryzen, Threadripper, Epyc).
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Staff Engineer, GPU Memory Architect Samsung Electronics9808 Scranton Rd, San Diego, CA, USA $151k–$151k8d Define, architect, and implement next-generation GPU memory subsystems and on-chip interconnects for Samsung's Exynos chipset to optimize performance, power, and area (PPA) for mobile and AI workloads.
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Principal Hardware Architect – ASIC & System Integration, Cisco Silicon One (Hybrid) CiscoMilpitas, California, US $234k–$234k8d Principal Hardware Architect driving ASIC system integration, signal/power integrity, and thermal design for high-performance networking silicon.
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Senior AI Silicon Architect MicrosoftUnited States, California, Mountain View 8d Provide technical leadership for early specification and architecture of silicon ASICs, specifically for AI accelerators, focusing on security, debug, telemetry, RAS, error handling, firmware/software interfaces, and power management.
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Manager, Digital Design AsteralabsSan Jose $216k–$216k8d Lead front-end digital design of high-performance PCIe, CXL, UAL, and ethernet devices for rack-scale AI infrastructure.
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Graduate Digital Design Engineer Renesas-ElectronicsEdinburgh, gb 8d Designing complex ASIC systems including digital control and data-path systems for automotive, industrial, infrastructure, and IoT applications.
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Memory Subsytem Expert, MLA Technology
AmazonAustin, Texas, United States
$159k–$215k9d
Design, validate, and operate memory subsystems (HBM, SRAM, UCIe) for next-generation machine learning chips and servers.
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Senior RISC-V Digital IP Design Engineer ON SemiconductorBrno, South Moravia, Czech Republic 9d Define and implement configurable RISC-V CPU IP for real embedded products, covering the full lifecycle from architectural exploration to tape-out.
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Digital IC Design Engineer | BGP Texas InstrumentsDallas, TX, United States 9d Define, develop, and refine the digital portion of battery gauge mixed signal SOCs, translating system intent into micro-architecture, RTL, and production-ready hardware.
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New College Grad - Engineer, ASIC Digital Design MicronMinneapolis, MN $86k–$86k9d Design and develop RTL for next-generation DRAM memory controllers and subsystems using SystemVerilog, supporting simulation, validation, and chip bring-up.
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Sr Principal VLSI Engineer↗ Hewlett Packard Enterprise | HpeSunnyvale, CA, US $174k–$353k9d Designs, analyzes, develops, and evaluates VLSI components and hardware systems, determining architecture and logic design while building physical implementations of complex integrated circuits.
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Distinguished Technologist, VLSI Engineering HpeSunnyvale, California, United States of America $183k–$390k9d Develops strategy and technology roadmaps for VLSI design and development engineering, acting as a lead authority to define industry standards and drive long-term technical goals.
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Physical Design Engineer↗ Micron TechnologyTlaquepaque, JAL, MX 9d Drive semicustom physical implementation from netlist handoff through tapeout for advanced semiconductor products.
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Senior Staff Digital Design Engineer MarvellIrvine, CA, US $136k–$201k9d Design high-performance digital ASICs for connectivity silicon powering AI data centers, focusing on high-speed datapaths, DSP pipelines, and protocol handling.
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Senior CPU RTL Design Engineer IntelUS, Texas, Austin $142k–$142k9d Design and optimize register transfer level (RTL) logic, simulation, and microarchitecture features for Intel's cutting-edge CPU processors.
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Sr Director, Hardware Engineering - Sydney Arista-NetworksSydney, NSW, au 9d Lead cross-functional teams in the design, verification, and manufacturing of high-density, high-bandwidth Cloud Networking Ethernet switches.
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Principal ASIC Package Design Engineer K2spacecorporationSeattle $200k–$200k10d Lead advanced ASIC package architecture and execution for high-performance mixed-signal and digital SoCs, focusing on flip-chip BGA and multi-chip module solutions.
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TPU PCIe Design Lead↗
GoogleSunnyvale, CA, US
$192k–$192k10d
Lead PCIe microarchitecture and RTL development for Google's next-generation Tensor Processing Units (TPUs) to power AI/ML workloads in data centers.
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SOC Design Engineer↗ QualcommMarkham, ON, CA $130k–$130k10d Design and develop next-generation power control systems and complex subsystems for high-performance, low-power ASICs and SoCs.
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Die-to-Die (D2D) Applications Engineer BroadcomUSA-Colorado-Fort Collins-4380 Ziegler Road $91k–$91k10d Primary technical resource for integrating and deploying proprietary Die-to-Die (D2D) PHY IP in silicon, bridging hardware, firmware, and software for customers developing ASICs for cloud computing AI engines, supercomputers, networking, and wireless…
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Senior Engineer II - Physical Design↗ Microchip TechnologyBurnaby, BC, CA $86k–$86k10d Senior Physical Design Engineer executing chip development methodologies for high-performance SOCs/ASICs, including block-level place and route, physical verification, and digital wrapper development.
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TPU SoC Integration Engineer, Cloud↗
GoogleSunnyvale, CA, US
$163k–$163k10d
Lead advanced SoC integration projects for multi-chiplet TPU architecture, managing RTL hierarchy up to the package level and collaborating with ASIC Packaging/Interposer teams.
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Senior FPGA Engineer DrwengAmsterdam 10d Design and implement low-latency, high-throughput FPGA applications for trading systems, managing the full development lifecycle from architecture to production support.
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Sr. Staff Engineer PD GlobalFoundriesIND - Karnataka - Bengaluru - North 11d Design and implement custom silicon solutions by executing physical design flows including synthesis, place-and-route, and verification to meet customer requirements.
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