ASIC Physical Design
2,710 open positions
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Physical Design Engineer AppleSan Diego, United States of America $175k–$263k5d Build full chip clock trees, perform specification generation, and clock planning involving design and construction of recombinant networks for high-performance CPU cores.
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SSD Systems Architect - Principal/MTS/SMTS/DMTS MicronBoise, ID - Main Site, US $153k–$351k5d Define innovative SSD architectures, develop product specifications, and model performance/power for next-gen memory solutions.
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Principal IC Digital Design Engineer↗ U-BloxCork, County Cork, Ireland 5d Lead the end-to-end development and delivery of integrated circuits for next-generation GNSS applications, coordinating architecture, design, verification, and validation across multiple disciplines.
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Hardware Engineering Technical Leader - ECAD - 10 to 15 years - Bangalore CiscoBangalore, India 5d Lead ECAD hardware design, layout, and routing for Cisco's core Switching, Routing, Wireless, and Industrial products.
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FY27 Intern - CPU Engineering Internship 2027 - 6 months, Cork↗ QualcommCork, County Cork, Ireland 5d Intern role supporting Snapdragon CPU teams in RTL design, verification, and power/performance analysis for advanced mobile chipsets.
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PCIe Switch Architect BroadcomUSA-Colorado-Colorado Springs-4420 Arrowswest Drive $144k–$230k5d Define, specify, and optimize PCIe architecture for industry-leading PCIe switch products, balancing power, performance, and area trade-offs.
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Senior CAD And Methodology Design Engineer Advanced Micro Devices, IncPenang, Malaysia 6d Design engineer supporting and optimizing the RTL-to-GDS design flow for semiconductor projects in the Adaptive & Embedded Computing Group.
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Expert FPGA / ASIC Numérique - Architecture ou Vérification - Industrie - Toulouse Sopra SteriaToulouse, Midi-Pyrenees, FR 6d Expert in FPGA/ASIC digital architecture or verification for critical embedded and industrial systems with real-time and safety constraints.
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Physical Design Engineer II MicrosoftUnited States, Washington, Redmond 6d Deliver high-quality physical design tasks including design planning, synthesis, placement, clock tree synthesis, static timing analysis, physical verification, IR drop, EM check, and formal equivalence checks at block, sub-chip, and full-chip levels.
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Principal FPGA & Hardware Developer↗ Ross VideoNepean, ON, CA CA$131k–CA$160k6d Develop FPGA, SoC, and high-speed hardware for professional live-video platforms, including board design, signal integrity, and embedded software integration.
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Silicon Design Lead OpenAISan Francisco 6d Lead silicon architecture, microarchitecture, and implementation of AI-native IP and subsystems, integrating hardware security mechanisms to power frontier AI models.
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RTL Engineer↗ Schweitzer Engineering Laboratories (sel)Burnaby, British Columbia, Canada 6d Develop and support SONET/VSN Multiplexers, Ethernet Circuit Emulation Gateways, Satellite Synchronized Network Clocks, and Ethernet Switches using VHDL RTL digital logic.
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Senior Lead Design Engineer - RTL Design AlteraSan Jose, California, United States $232k–$330k6d Lead RTL architecture, microarchitecture, and implementation for complex FPGA, programmable SoC, and infrastructure-class subsystems, translating system requirements into robust microarchitectures and guiding execution from concept through product readiness.
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Senior/Staff Physical Design Engineer MediaTekBangalore 6d Senior Block Coordinator responsible for planning, execution, and closure of 15+ ASIC/SoC blocks using Cadence Innovus.
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Senior Engineer, SoC HAL
AmazonCupertino, California, United States
$168k–$262k6d
Design and implement the Hardware Abstraction Layer (HAL) and driver stack for custom silicon chips, bridging hardware and system software.
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Principal SoC Design Engineer ArmSan Diego, California $250k–$338k6d Designing complex compute subsystems and System-on-Chips (SoCs) by integrating IP blocks, developing micro-architecture, and ensuring timing closure.
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Staff Engineer- DFT MarvellSanta Clara, CA, US $114k–$171k6d Design and implement DFT methodology and flow for next-generation optical DSP ASICs in hyperscale data center and AI infrastructure markets.
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ASIC Principal Design Engineer HpeHeredia, Heredia, Costa Rica 6d Designs, analyzes, develops, modifies, and evaluates VLSI components and hardware systems; determines architecture and logic design, conducts design verification, and builds physical implementations of complex integrated circuits.
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Systems Solutions Architect CadenceSAN JOSE, US $186k–$345k6d Define compute-centric SoC subsystems for Physical AI applications, optimizing for power, performance, area, and software flexibility.
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Principal ASIC/System-on-Chip Engineer↗ Frontgrade GaislerGothenburg, Västra Götaland County, Sweden 6d Lead the complete development of space microprocessor System-on-Chip designs from architectural design to implementation and validation.
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Principal PCS/PMA RTL Design Engineer AsteralabsSan Jose $185k–$240k6d Design and implement synthesizable RTL for Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) logic in high-speed interconnect standards (Ethernet, PCIe, UCIe, UALink) for AI and cloud infrastructure ASICs.
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Logic Design Engineer Quantum MachinesBudapest, Hungary 7d Designing configurable, low-latency RTL and optimizing FPGA logic & timing for quantum computing control systems.
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Senior Digital Design Engineer Renesas-ElectronicsCatania, it €37k–€50k7d Design and implement digital blocks in Verilog/SystemVerilog for next-generation power management solutions targeting AI, Cloud, and Data Center applications.
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R&D Engineering, Principal Engineer↗ SynopsysKA, IN 7d Principal Engineer responsible for timing signoff methodology, static timing analysis, and standard cell library development for advanced semiconductor nodes.
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