Senior Staff Engineer, Physical Design
Core
Drive RTL-to-GDS implementation for next-generation processors and ASICs powering AI infrastructure, cloud data centers, and networking solutions.
Role type
Senior Staff Physical Design Engineer
Builds
Advanced silicon chips (processors and ASICs)
Domain
Semiconductor / Digital IC Design
Required skills
RTL-to-GDS flow, Synthesis, Place & Route, Static Timing Analysis (STA), Tcl, Perl, Python, Verilog/VHDL
Technologies
Tcl, Perl, Python, Verilog, VHDL
Responsibilities
Drive RTL-to-GDS implementation including synthesis, place & route, and timing closure; Perform timing and logic ECOs to achieve PPA targets; Debug and resolve timing, congestion, and implementation challenges; Develop and enhance physical design methodologies and automation flows; Collaborate with RTL, architecture, timing, and CAD teams.
Seniority
Senior Staff, hands-on IC
