Senior Silicon Architect – Cache Coherent Interconnects
Core
Design silicon architecture and construction plans for next-generation CPU processors, focusing on dielet partitioning, packaging, and die-stacking exploration.
Role type
Senior IC silicon architect (CPU)
Builds
CPU processors for consumer graphics, self-driving cars, and AI
Domain
Semiconductor / High-performance computing
Deliverable
production ML models
Required skills
CPU system architecture, ASIC floor-planning, digital design, cache coherency, high-speed interconnects, advanced packaging (InFO, CoWoS, EMIB), through-silicon via, backside power delivery
Preferred skills
Dielet, Interposer, Substrate connectivity
Responsibilities
Own silicon architecture and construction plan for next-gen CPUs; explore 2D/2.5D/3D hybrid-bonded dielet constructions; develop early floorplans and plan die-to-die/off-chip IO (UCIe, DRAM, PCIe); collaborate with architecture, logic, physical design, and packaging teams to meet area, performance, power, and thermal goals.
Seniority
Senior, hands-on IC
