Senior/ Staff Physical Design Engineer
Core
Architecting the physical implementation of complex semiconductor chips for AI infrastructure connectivity, transforming logic into high-performance silicon.
Role type
Senior/Staff Physical Design Engineer (Backend)
Builds
Custom connectivity solutions (CXL, Ethernet, NVLink, PCIe, UALink) for hyperscalers and AI clusters
Domain
Semiconductor / AI Infrastructure / High-Speed Connectivity
Deliverable
production ML models
Required skills
Physical Design (Synthesis, Floorplanning, Place & Route, CTS), Timing Signoff (STA), Physical Verification (DRC/LVS), Reliability Analysis (EMIR), Logic Equivalence Checking (LEC), Advanced Process Nodes (7nm and below), EDA Scripting (TCL/Python)
Preferred skills
Full-chip implementation, Power/Noise Analysis (SI/PI), Design-for-Test (DFT), High-speed interface protocols, Synopsys Fusion Compiler/ICC2, Cadence Innovus
Technologies
Synopsys Fusion Compiler, ICC2, Cadence Innovus, TCL, Python
Responsibilities
Establish local execution culture and technical standards for the Israel R&D center, own the full physical implementation journey from synthesis to signoff, drive design integrity through rigorous STA, DRC/LVS, and EMIR analysis, develop backend methodologies and automate EDA tool flows, collaborate with Architecture and DFT teams on advanced process nodes
Seniority
Senior/Staff, hands-on IC
