IC Design Engineer (STA/ Synthesis)
Core
Lead STA/Synthesis engineer responsible for timing closure, constraint development, and validation of mission-critical IP and ASIC blocks in advanced technology nodes.
Role type
Senior IC Design Engineer (STA/Synthesis)
Builds
High-speed, complex digital and mixed-signal ASIC blocks and SoC designs
Domain
Semiconductor / ASIC Design
Required skills
Static Timing Analysis (STA), Synthesis, Clock Tree Synthesis, Timing Constraint Development, Static Equivalence Checks, Low Power Design, Tcl/Perl Scripting, Process Corner Analysis, Timing ECO Generation
Preferred skills
RTL Design, Place-and-Route, Hierarchical Design Flows
Technologies
PrimeTime, Tempus, DC-T, Genus, Fishtail, VCLP, Formality
Responsibilities
Develop and validate timing constraints for SoC designs; Perform static timing analysis (STA) using industry-standard tools; Perform synthesis and run static audits (CDC, RDC, Low Power, equivalence); Define and implement timing signoff methodologies; Conduct pre-route timing checks and QoR analysis; Automate timing analysis processes using scripting languages; Provide guidance on clock tree synthesis and optimization; Generate timing ECOs for timing closure; Drive timing closure for complex IP and ASIC blocks
Seniority
Senior, hands-on IC
