Lead FPGA Timing & Characterization Silicon Design Engineer
Core
Lead the development, validation, silicon correlation, and release of FPGA timing models to enable industry-leading FPGA implementation and timing analysis tools.
Role type
Senior Member of Technical Staff (SMTS), Lead FPGA Timing & Characterization Silicon Design Engineer
Builds
Production-quality FPGA timing libraries and characterization flows
Domain
Semiconductor / FPGA Design / Digital Logic
Required skills
FPGA architecture and timing closure, Static Timing Analysis (STA), PVT variation and timing margins, OCV/POCV methodologies, silicon characterization and model generation flows, scripting and automation (Python, Perl, Tcl), debugging and root-cause analysis, large-scale flow automation, data analytics, Vivado or Quartus tools, statistical timing techniques
Preferred skills
Leading cross-functional technical initiatives, mentoring engineers, establishing engineering best practices, influencing roadmaps and strategies
Technologies
Vivado, Quartus, Python, Perl, Tcl
Responsibilities
Establish validation frameworks for FPGA timing library quality, drive root-cause analysis for timing discrepancies, develop and maintain regression suites and DRC checks, drive characterization of FPGA resources, develop automation flows to improve timing quality, own planning and execution of Timing Library releases, perform QoR analysis on Vivado software, coordinate release readiness reviews, provide technical status updates to engineering leadership
Seniority
Senior, hands-on IC with mentorship responsibilities
