Staff Engineer - DFT
Core
Design for Test (DFT) and Static Timing Analysis (STA) engineering for networking SoCs, covering timing constraints, testability strategy, and verification across copper and optical products.
Role type
Staff Engineer - DFT/STA
Builds
Networking SoCs (copper and optical)
Domain
Semiconductor / Networking
Required skills
SCAN/ATPG/JTAG/MBIST, Tile/Chip level STA flows, Gate level simulations, Test structures & ATPG fault models, Scan insertion techniques, Test mode timing constraints, Memory BIST generation, Perl/Tcl scripting
Preferred skills
Synopsys/Mentor tools, IEEE1149.1/6 standards, Post-Si ATE debug
Technologies
Synopsys, Mentor, Perl, Tcl
Responsibilities
Develop timing constraints and technology library infrastructure, define and implement DFT/STA flows, perform DFT/STA verification and post-Si bring up, collaborate with Logic/Physical design/STA/ATE teams, resolve cross-domain DFT issues, generate and verify Memory BIST.
Seniority
Staff, hands-on IC
