Physical Design Engineer
Core
Physical Design Engineer responsible for ASIC/SoC design implementation, focusing on place and route, timing closure, and physical verification to achieve Right-first time silicon.
Role type
Senior IC physical design engineer (ASIC/SoC)
Builds
ASIC/SoC chips for Broadcom's product portfolio
Domain
Semiconductor / VLSI Design
Required skills
place and route, timing analysis (STA), floor-planning, partitioning, clock tree synthesis, physical verification (LVS/DRC), ECO implementation, constraint development and validation
Preferred skills
formal verification, 7nm and lower technology tapeout experience, Primetime, ICC2, Innovus, Caliber, LEC
Technologies
Primetime, ICC2, Innovus, Caliber, LEC
Responsibilities
Perform floor-planning, partitioning, placement, clock tree synthesis, routing, and timing closure; Drive tools and methodologies to achieve PPA metrics; Complete equivalence checks and timing analysis; Implement timing and functional ECOs; Conduct physical verification (LVS/DRC)
Seniority
Senior, hands-on IC
