ASIC Engineer, Physical Design CAD
Core
Building and owning the physical design flow infrastructure (synthesis, place and route, timing closure) for custom AI and data center silicon.
Role type
Senior IC ASIC Physical Design CAD Engineer
Builds
Automated physical design flows and infrastructure for tapeout programs
Domain
Semiconductor / ASIC Physical Design / EDA
Deliverable
production ML models
Required skills
Python, Tcl, EDA flow automation, digital physical design implementation, synthesis, place and route, timing closure, commercial EDA tools (Fusion Compiler, Genus, Innovus, PrimeTime, Tempus, StarRC), version control
Preferred skills
Power integrity, EM/IR analysis, physical verification, timing constraint development, data pipeline building, AI/LLM tooling application, hierarchical design planning
Technologies
Python, Tcl, Fusion Compiler, Genus, Innovus, PrimeTime, Tempus, StarRC, SDC
Responsibilities
Develop and maintain digital physical design flow stages; Build and extend flow automation integrated with build and CI infrastructure; Debug flow and QoR issues with design leads; Qualify and integrate commercial EDA tools; Build constraint and netlist validation capabilities; Develop QoR tracking metrics and dashboards; Write flow documentation and support designers
Seniority
Senior, hands-on IC
