Sr. Staff Engineer, Physical Design
Core
Lead an experienced team of physical design and static timing analysis engineers to deliver backend design services for next-generation 5G, cloud, enterprise, and automotive SOC designs.
Role type
Senior IC physical design manager
Builds
Complex low-power, high-speed System-on-Chip (SOC) designs for data infrastructure
Domain
Semiconductor / ASIC Physical Design
Required skills
hierarchical physical design strategies, deep sub-micron technology (N7/N5), ASIC design flow, Verilog HDL, synthesis, timing closure, Makefile/Tcl/Perl scripting, Cadence suite (Genus, Innovus), Synopsys suite (IC Compiler, Fusion Compiler)
Preferred skills
static timing analysis (Tempus, PrimeTime), EM/IR-Drop/crosstalk analysis (Voltus, PTSI, Apache, AstroRail, PrimeRail), extraction (QRC, StarRC), formal or physical verification (LEC, Formality, Calibre)
Responsibilities
Lead physical design and STA teams, provide backend design services (floor planning, power grid, place and route, clock tree synthesis, timing closure, signoff, verification), interact with customers and worldwide teams, develop physical design methodology and flow
Seniority
Senior, hands-on IC with management responsibilities
