ASIC Physical Design
2,686 open positions
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Senior Custom ASIC Engineering Lead BroadcomUSA-CA San Jose Innovation Drive $144k3mo Lead external and internal cross-functional teams in physical design, STA, DFT, and packaging for Broadcom's critical infrastructure chips.
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SDE - CPLD / FPGA
AmazonSeattle, Washington, United States
$144k–$194k3mo
Design, implement, verify, validate, deploy, and support programmable logic components (CPLD/FPGA) for AWS server infrastructure to ensure operational excellence and fleet health.
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Senior Principal Engineer – Hardware Chip Lead, Connectivity BU MarvellSanta Clara, CA $182k–$273k3mo Lead end-to-end hardware design and program delivery for advanced optical DSP ASICs serving hyperscale data center, enterprise, and AI infrastructure markets.
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Senior Engineer, Physical Design Engineering (ASIC) AnalogdevicesUS, NJ, Somerset $117k3mo Senior Physical Design Engineer responsible for implementing complex digital and mixed-signal IC designs from floorplanning through tapeout.
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CPU Microarchitect/RTL Engineer - Fetch, Out of Order AppleSanta Clara, United States of America 3mo Design high-performance, low-power CPU front-end and out-of-order subsystems for Apple Silicon products.
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Senior Physical Design Engineer MicrosoftUnited States, Oregon, Hillsboro 3mo Drive end-to-end execution from synthesis through place-and-route for large System-on-Chip (SOC) designs, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
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Physical Design Methodology & Flow SambanovasystemsSan Jose, CA $180k3mo Lead the development and maintenance of physical design composition flows for state-of-the-art RDU chips optimized for machine learning and artificial intelligence.
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Senior/ Staff Physical Design Engineer AsteralabsTel Aviv 3mo Architecting the physical implementation of complex semiconductor chips for rack-scale AI infrastructure, transforming logic into high-performance silicon.
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Physical Design Engineer↗ AMDVancouver, British Columbia, Canada 3mo Lead engineer driving PPA improvements for critical graphics blocks, serving as the main point of contact from Physical Design to RTL teams.
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<Data center>System Expert for Post-silicon including SLT MediaTekHsinChu 3mo System design, development, and post-silicon validation for customized ICs in Enterprise/AI/xPU, focusing on high-speed physical layer data transmission and mass production support.
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IP RTL Senior Design Engineer IntelIndia, Bangalore 3mo Develop high-quality intellectual property (IP) logic designs, register transfer level (RTL) coding, and simulations for Unified Intel Chassis designs, focusing on protocol bridges, access control, and reliability features.
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Senior ASIC Design Engineer HpVancouver, Washington, United States of America $116k3mo Lead functional blocks and subsystems of digital ASICs from design to silicon verification for HP's main controller and proprietary IP in printers.
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ASIC Design Engineer - Tel-Aviv Office MicronIsrael 3mo Develop digital and mixed-signal blocks from specification through RTL implementation, focusing on power-efficient, implementation-aware design for advanced flash memory products.
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Principal Technical Program Manager – DSP/Mixed-Signal ASIC Development – TeraWave BlueoriginSan Diego, CA $249k3mo Lead end-to-end development of advanced mixed-signal/DSP ASICs and SoCs (including Digital Beamforming) for TeraWave's satellite communication system, spanning architecture definition through production.
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Staff Chip Design Engineer - AI↗ CognichipToronto, Ontario, Canada 3mo Staff Chip Design Engineer bridging AI solutions with silicon design workflows, optimizing chip flows and generating hardware datasets for model robustness.
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HBM Logic Architect SkhynixamericaSan Jose, CA $150k3mo Establishing US-based HBM Architect Design team to address base-die architectural challenges in HBM and 3D-stacked DRAM for key customers.
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Staff PCIe Design Engineer ArmToronto, Canada $159k3mo Designing and integrating PCIe, CXL, and other I/O subsystems into System-on-Chips (SoCs) for compute platforms.
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Systems Architect AmbiqmicroincSingapore 3mo Define high-level architecture for Ambiq's low-power System-on-Chips (SoCs), focusing on subsystems and interfaces for audio, imaging, display, and high-speed links to enable ubiquitous AI at the edge.
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Staff Engineer, FPGA Design (R5347) ShieldaiSeattle, Washington 3mo Designing, implementing, verifying, and debugging FPGA-based solutions for complex avionics in Unmanned Aerial Vehicles (UAV).
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System Design Intern, LDE - 2027 NVIDIATaiwan, Taipei 3mo Design and development of next-generation products including Datacenter, GeForce, Virtualization, and Automotive products based on GPUs, DPUs, CPUs, and LPUs.
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AI/ML driven ASIC Design and Implementation Lead Engineer NxpBangalore 3mo Lead engineer exploring and implementing AI/ML techniques to improve efficiency, power, performance, and area for SoC and IP development flows.
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Sr Principal HW Design Engineer/HW Architect CadenceSAN JOSE $179k3mo Architect and design hardware system platforms for emulation-acceleration technologies, managing board-level design, schematic entry, PCB layout, and signal integrity.
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FPGA Lead/Architect/Implementor FlirDenmark - Kongens Lyngby 3mo Lead the architecture, design, and implementation of next-generation ultra-high-speed Ethernet test platforms supporting IEEE802.3dj and Ultra Ethernet standards.
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