Senior Engineer, Physical Design Engineering (ASIC)
Core
Senior Physical Design Engineer responsible for implementing complex digital and mixed-signal IC designs from floorplanning through tapeout.
Role type
Senior IC physical design engineer (ASIC/SoC)
Builds
Complex digital blocks, subsystems, and top-level IC implementations
Domain
Semiconductor / ASIC Physical Design
Deliverable
production ML models | product features
Required skills
Floorplanning, place-and-route, clock tree synthesis, timing closure, physical verification (DRC/LVS/ERC), power optimization, signal integrity analysis, TCL/Python scripting, cross-functional collaboration
Preferred skills
Advanced-node implementation, low-power design methodologies, mixed-signal integration, backend flow automation, technical mentoring
Technologies
Cadence-based flows, industry-standard physical design and signoff tools
Responsibilities
Own physical design implementation for complex blocks including floorplanning, placement, CTS, routing, and optimization; Drive timing closure, congestion analysis, and power/area improvements; Perform physical verification and reliability checks; Develop constraints, scripts, and flow improvements; Collaborate with RTL, STA, DFT, and verification teams to resolve issues; Analyze and debug timing, signal integrity, and power issues; Mentor junior engineers on physical design practices; Support tapeout planning and execution
Seniority
Senior, hands-on IC