Physical Design/CAD Engineer
Core
Drive planning, coordination, and execution for the design of connectivity ASICs used in cloud service providers and network OEMs, ensuring robust full-chip signoff from RTL to GDS.
Role type
Senior IC Physical Design/CAD Engineer
Builds
World-class EDA tool flows and connectivity ASICs for hyperscalers and ecosystem partners
Domain
Semiconductor / AI Infrastructure / Connectivity (CXL, Ethernet, NVLink, PCIe)
Deliverable
production ML models | product features
Required skills
PnR, Extraction, Timing closure, EM-IR, Formality, DRC/LVS, Synthesis, Place-and-route, Advanced node design (7nm or below), Cadence/Synopsys toolchains, Scripting (Tcl, Python, Perl)
Preferred skills
Agentic AI solutions, EDA/IP vendor integration, High-speed SERDES/Ethernet PHY timing, ECO methodologies, DFT tools
Technologies
Cadence, Synopsys, CXL, Ethernet, NVLink, PCIe, UALink, COSMOS
Responsibilities
Support and build flows for world class EDA tools; Drive Physical Design flow activities ensuring robust signoff; Architect and recommend flow improvements; Work with cross function teams to define requirements for best PPA; Own a small block partition and closure; Partner with design and verification teams for block/top convergence
Seniority
Senior, hands-on IC
